tangxifan
|
3b2a4c5387
|
[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
|
2020-11-22 20:25:03 -07:00 |
|
tangxifan
|
dcb50e4f19
|
[Tool] Use use standard data structure to store global port information
|
2020-11-10 19:07:28 -07:00 |
|
tangxifan
|
5bcd559851
|
[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
|
2020-10-30 17:29:04 -06:00 |
|
tangxifan
|
0d77916041
|
[Tool] Support multi-region frame-based configuration protocol
|
2020-10-30 10:43:11 -06:00 |
|
tangxifan
|
448e88645a
|
[Tool] Support multiple memory banks in top-level module
|
2020-10-29 12:42:03 -06:00 |
|
tangxifan
|
e988e35f81
|
[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
|
2020-09-29 12:22:10 -06:00 |
|
tangxifan
|
154f23b108
|
[OpenFPGA Tool] Add self-testing Verilog codes for configuration done signals in full testbenches
|
2020-09-26 11:54:06 -06:00 |
|
tangxifan
|
1b4e449179
|
[OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol
|
2020-09-25 21:05:20 -06:00 |
|
tangxifan
|
8468f25b23
|
[OpenFPGA Tool] Bug fix in the smart fast configuration strategy
|
2020-09-24 16:31:55 -06:00 |
|
tangxifan
|
46b12611a9
|
[OpenFPGA Tool] Bug fix for smart fast configuration
|
2020-09-23 22:04:07 -06:00 |
|
tangxifan
|
154c9045f6
|
[OpoenFPGA Tool] Bug fix for smart fast configuration
|
2020-09-23 21:38:42 -06:00 |
|
tangxifan
|
c2c37d7555
|
[OpenFPGA Tool] Add more print-out for smart fast configuration
|
2020-09-23 21:34:23 -06:00 |
|
tangxifan
|
a3abf81afe
|
[OpenFPGA Tool] Support on set signals and smart selection between reset and set signal for fast configuration
|
2020-09-23 21:25:06 -06:00 |
|
tangxifan
|
064678fe32
|
[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
|
2020-09-23 20:27:52 -06:00 |
|
tangxifan
|
ad881ea4dc
|
[OpenFPGA Tool] Bug fix for Verilog testbench using frame-based /memory bank
|
2020-09-23 18:59:25 -06:00 |
|
tangxifan
|
eb070694b5
|
fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
|
2020-07-15 17:52:41 -06:00 |
|
tangxifan
|
66a50742fc
|
use configuration chain in the k4k4 test case to speed up CI
|
2020-07-15 11:56:11 -06:00 |
|
tangxifan
|
3f14fe62c7
|
add fast configuration support for configuration chain protocol
|
2020-07-15 11:44:23 -06:00 |
|
tangxifan
|
6ea857ae6c
|
use fast method to inquire number of bits and blocks in bitstream databases
|
2020-07-03 10:55:25 -06:00 |
|
tangxifan
|
9f19c36a89
|
use char in fabric bitstream to save memory footprint
|
2020-07-02 15:56:50 -06:00 |
ganeshgore
|
559564c333
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2020-06-12 17:31:14 -06:00 |
|
tangxifan
|
5368485bd6
|
keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
0bee70bee6
|
finish memory bank configuration protocol support.
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
e14c39e14c
|
update Verilog full testbench generation to support memory bank configuration protocol
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
8ec8ac4118
|
bug fixed in flatten memory organization. Passed verification
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
b9aac3cbdf
|
updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
9e176b8d38
|
add fast configuration stats to log
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
8b3e79766c
|
add fast configuration option to fpga_verilog to speed up full testbench simulation
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
b5e5182f52
|
frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
bdc9efb38f
|
bug fix in top-level testbench for frame-based decoders
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
6a72c66eb8
|
bug fixed for frame-based configuration memory in top-level full testbench
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
ece651ade2
|
bug fixed in the configuration chian errrors
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
cff5b5cfc1
|
break the configuration testbench. This commit is to spot which modification leads to the problem
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
4a0e1cd908
|
add fabric bitstream data structure and deploy it to Verilog testbench generation
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
bba476fef4
|
add explicit port mapping support to Verilog testbench generator
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
1e2226e1c3
|
now use explicit port mapping in the verilog testbenches for reference benchmarks
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
8f5a684b10
|
removed redundant include files in all the verilog netlists except the top one
|
2020-06-11 19:28:13 -06:00 |
|
tangxifan
|
185e574738
|
removed redundant include files in all the verilog netlists except the top one
|
2020-04-24 20:21:32 -06:00 |
|
tangxifan
|
2ffd174e6a
|
fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
|
2020-04-15 15:48:33 -06:00 |
|
tangxifan
|
3369d724e9
|
bug fixing in Verilog top-level testbench generation
|
2020-04-05 17:50:11 -06:00 |
|
tangxifan
|
decc1dc4b2
|
debugged global gp input/output port support
|
2020-04-05 17:39:30 -06:00 |
|
tangxifan
|
80bb2baae5
|
start verification and bug fixing
|
2020-02-28 14:29:01 -07:00 |
|
tangxifan
|
ae899f3b11
|
bug fixed for clock names
|
2020-02-27 16:51:55 -07:00 |
|
tangxifan
|
9b769cd8e4
|
bug fix for using renamed i/o names
|
2020-02-27 16:37:20 -07:00 |
|
tangxifan
|
77529f4957
|
adapt top Verilog testbench generation
|
2020-02-26 21:30:21 -07:00 |