tangxifan
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ab53f88c2b
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[test] now use a fixed device layout for the single-mode LUT design testcase
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2022-10-04 10:05:22 -07:00 |
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tangxifan
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4eaecde0b9
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[test] add golden netlists to ensure no cout in gsb
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2022-10-01 11:03:13 -07:00 |
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tangxifan
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78f30cf072
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[test] add a new test to track the golden netlists where cout is not in GSB
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2022-09-30 15:38:27 -07:00 |
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tangxifan
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0565ca7aca
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[script] add missing files
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2022-09-29 16:14:38 -07:00 |
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tangxifan
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a3e7133d63
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Merge branch 'master' into wire_lut_test
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2022-09-29 16:02:18 -07:00 |
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tangxifan
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ce0fbe1765
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[test] fixed a few bugs
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2022-09-29 15:32:31 -07:00 |
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tangxifan
|
9bc9b61d35
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[test] fixed a few bugs
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2022-09-29 15:11:30 -07:00 |
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tangxifan
|
f5e7ec4dd1
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[test] add a new test case to validate wire lut case
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2022-09-29 14:28:59 -07:00 |
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tangxifan
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3f8e2ade2e
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[script] update missing scripts required by pb_pin_fixup test cases
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2022-09-29 13:39:46 -07:00 |
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tangxifan
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49fa783914
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[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
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2022-09-29 10:45:27 -07:00 |
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tangxifan
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79b260f5e1
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[arch] update missing arch
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2022-09-21 16:52:32 -07:00 |
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tangxifan
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b1f8cdab3c
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[test] update missing arch files which are not placed in the openfpga_flow/vpr_arch
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2022-09-21 15:28:56 -07:00 |
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tangxifan
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b532bca9d2
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[script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment
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2022-09-21 10:54:16 -07:00 |
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tangxifan
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36603f9772
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Merge branch 'master' into vtr_upgrade
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2022-09-20 21:08:06 -07:00 |
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tangxifan
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b8f1520367
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[test] fixed a bug
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2022-09-20 18:12:23 -07:00 |
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tangxifan
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4e254a304d
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[test] now golden netlists have no relationship with OPENFPGA_PATH
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2022-09-20 18:10:52 -07:00 |
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tangxifan
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5e23be19a5
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[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
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2022-09-20 18:07:31 -07:00 |
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tangxifan
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1b0b50b928
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[test] update golden netlist
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2022-09-20 16:04:05 -07:00 |
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tangxifan
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b630d60b7e
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[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed
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2022-09-20 14:14:18 -07:00 |
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tangxifan
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37c5056d6a
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[test] now use a fixed routing channel width for quicklogic tests
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2022-09-20 12:25:40 -07:00 |
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tangxifan
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846ca26311
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[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
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2022-09-20 12:08:24 -07:00 |
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tangxifan
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40663f956c
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[test] relax counter128 required routing width from 50 to 60; Seem that VTR has some loss in routability
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2022-09-19 21:55:15 -07:00 |
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tangxifan
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10e86d334a
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[test] add test cases to validate the various layouts where I/Os are in the center of the grid
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2022-09-16 10:29:19 -07:00 |
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tangxifan
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330785635d
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[test] now use a bigger fabric for the test case on custom I/O location
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2022-09-13 17:53:33 -07:00 |
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tangxifan
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0d6e4e3979
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[test] add a new example for the repack options
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2022-09-12 16:21:49 -07:00 |
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tangxifan
|
1ab7590603
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[test] added a new test case to
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2022-09-09 16:59:06 -07:00 |
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tangxifan
|
d4523e819c
|
[test] fixed a bug
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2022-09-08 16:55:50 -07:00 |
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tangxifan
|
d76f3e3b6c
|
[test] fixed the bug
|
2022-09-08 16:34:23 -07:00 |
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tangxifan
|
218e6d0a47
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[arch] fixed syntax errors
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2022-09-08 16:31:52 -07:00 |
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tangxifan
|
a840aeea7a
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[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
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2022-09-08 16:27:11 -07:00 |
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tangxifan
|
477e2119d7
|
[test] remove abs paths in golden outputs without time stamps
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2022-09-06 15:24:43 -07:00 |
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tangxifan
|
93ab992187
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[test] update golden outputs without time stamps
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2022-09-06 14:59:00 -07:00 |
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tangxifan
|
561d0a6545
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[test] add more test case to track golden outputs for representative fpga sizes
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2022-09-06 14:04:23 -07:00 |
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tangxifan
|
c48f750f86
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[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
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2022-09-01 20:10:29 -07:00 |
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tangxifan
|
51dc082bd4
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[test] force a fixed routing chan W for no time stamp test case
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2022-09-01 15:02:40 -07:00 |
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tangxifan
|
d86eb04c5d
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[test] now no timestamp test case covers gsb files
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2022-09-01 14:03:51 -07:00 |
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tangxifan
|
069e2b00b1
|
[test] add more test cases to validate gsb options
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2022-08-29 22:03:06 -07:00 |
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tangxifan
|
8b17bf1b1c
|
[test] add a new test case to validate that .act file is not required when power analysis flow is off
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2022-08-01 18:44:47 -07:00 |
|
tangxifan
|
35fe858035
|
[test] fixed a few bugs
|
2022-07-28 12:06:16 -07:00 |
|
tangxifan
|
ca9122ddb9
|
[test] fixed a bug
|
2022-07-28 11:57:47 -07:00 |
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tangxifan
|
ec31e124b7
|
[test] reworked test case on pcf2place
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2022-07-28 11:51:56 -07:00 |
taoli4rs
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cfc0d08060
|
Add constrain_pin_location command in openfpga; add full flow test.
|
2022-07-20 11:51:00 -07:00 |
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tangxifan
|
9832722056
|
[test] now add QuickLogic memory bank to fpga bitstream regression tests
|
2022-05-25 11:42:32 +08:00 |
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tangxifan
|
86347a9d49
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[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
|
2022-05-25 11:19:49 +08:00 |
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tangxifan
|
6719a9aa26
|
[test] update golden netlists/testbenches etc.
|
2022-05-22 13:03:01 +08:00 |
|
tangxifan
|
22c4d72358
|
[test] add a test case to validate negative edge-triggered ff
|
2022-05-09 16:57:42 +08:00 |
Ganesh Gore
|
522982c9ba
|
Adde vtr_benchmarks_template for demo
|
2022-05-06 22:40:36 -06:00 |
|
Ganesh Gore
|
275cda081e
|
[Bugfix] Typo
|
2022-05-05 08:40:21 -06:00 |
|
Ganesh Gore
|
e845b62322
|
Update regession tasks
|
2022-05-05 01:46:19 -06:00 |
|
Ganesh Gore
|
21c3dbf611
|
Added regression for template project
|
2022-05-02 23:23:45 -06:00 |