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249 Commits

Author SHA1 Message Date
tangxifan dd0680246a [Doc] Typo fix on fabric key command 2021-01-25 14:12:40 -07:00
ganeshgore 1ba7e0663f
Merge pull request #176 from lnis-uofu/dev 
Documentation Formatting
 2021-01-24 21:11:49 -07:00
tangxifan e18c533657 [Doc] Add new openfpga shell command to documentation 2021-01-24 14:48:56 -07:00
tangxifan 815468ac65 [Doc] Add shortcut to call pin constraint option to documentation 2021-01-20 09:20:51 -07:00
tangxifan 977ff52cb1 [Doc] Format openfpga command documentation by using option views 2021-01-19 20:26:38 -07:00
tangxifan e9dc708d66 [Doc] Group file format documentation into a unified section 2021-01-19 19:44:44 -07:00
tangxifan ac8c63553a [Doc] Add file format index file 2021-01-19 18:07:53 -07:00
tangxifan fbb5c0cf8f [Doc] Add pin constraints to documentation 2021-01-19 18:04:45 -07:00
tangxifan c7f02601ab [Doc] Add repack design constraints to documentation 2021-01-17 12:59:46 -07:00
tangxifan c4d3e7c50c [Doc] Update documentation for the new XML syntax in simulation settings 2021-01-15 12:30:26 -07:00
tangxifan 0c808bec41 [Doc] Add clarification for defining multi-bit global tile ports 2021-01-09 20:00:16 -07:00
tangxifan 2324edc522 [Doc] Update documentation for upgraded tile annotation 2021-01-09 18:55:16 -07:00
tangxifan 226f6b8d6d [Doc] Update documentation about FF circuit models to show capability in modeling SCFFs 2021-01-04 18:30:04 -07:00
Lalit Sharma 3ccd6b80dd Updating compile.rst file with updated compilation steps 2020-12-13 21:04:10 -08:00
tangxifan 406edeec89 [Doc] Typo fix 2020-12-04 15:07:02 -07:00
tangxifan 4fe190fa7e [Doc] Bug fix in LUT circuit model documentation 2020-12-04 14:44:27 -07:00
tangxifan 8350b0f911 [Doc] Update documentation about default value definition in tile annotation 2020-12-02 17:08:34 -07:00
tangxifan cc0114459a [Doc] Enrich examples for LUT circuit models 2020-11-26 13:03:12 -07:00
tangxifan 62e804215b [Doc] Add svg figures for LUT examples 2020-11-26 12:35:39 -07:00
tangxifan b857135f4e [Doc] Add clarification about which cells are applicable for signal initialization 2020-11-23 15:19:15 -07:00
tangxifan 2b9a97729e [Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models 2020-11-23 15:09:47 -07:00
tangxifan fd0e6814ea [Doc] Update documentation about the pre-processing flags 2020-11-22 20:33:15 -07:00
tangxifan f6126d1ed6 [Doc] Add illustrative example to diff between global ports definitions 2020-11-12 09:24:39 -07:00
tangxifan bc43c876b0 [Doc] Update documentation for the rules in global port definition for tile ports 2020-11-11 14:10:11 -07:00
tangxifan 2c269c532a [Doc] Update doc for the global port definition using physical tile port 2020-11-10 20:48:28 -07:00
tangxifan 056b7c0c79 [Doc] Update documentation about CCFF circuit model examples 2020-11-06 12:22:22 -07:00
tangxifan 55b14fa6b4 Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA into dev 2020-11-06 10:11:38 -07:00
tangxifan 849ecc7fc0 [Doc] Add notes for using the is_data_io syntax 2020-11-05 09:30:19 -07:00
tangxifan 9bce2f3818 [Doc] Update documentation for new XML syntax "is_data_io" 2020-11-05 09:28:46 -07:00
tangxifan 032cbfb8b2
Merge pull request #113 from LNIS-Projects/dev 
Multi-region support on Frame-based Configuration Protocol
 2020-10-31 10:37:38 -06:00
tangxifan be7f7592ae [Doc] Update documentation about don't care bit in frame address 2020-10-30 22:13:28 -06:00
tangxifan 7e940980e1 [Doc] Update documentation about configuration regions for frame-based protocol 2020-10-30 21:52:01 -06:00
Laboratory for Nano Integrated Systems (LNIS) cd0d3dd798
Merge pull request #112 from LNIS-Projects/dev 
Multi-region Memory Bank Configuration Protocol Support
 2020-10-29 18:39:44 -06:00
tangxifan c2c384e24b [Doc] update documentation about memory bank definition 2020-10-29 17:04:25 -06:00
Laboratory for Nano Integrated Systems (LNIS) ff9c17cba8
Merge pull request #111 from LNIS-Projects/dev 
Bug fix in tutorial due to renamed regression tests
 2020-10-28 09:40:28 -06:00
tangxifan efb0162e3f [Doc] Bug fix in tutorial due to renamed regression tests 2020-10-28 08:58:19 -06:00
Laboratory for Nano Integrated Systems (LNIS) 16128f0905
Merge pull request #107 from LNIS-Projects/dev 
Enable Customized Fabric Netlist Location in Verilog Testbench Generation
 2020-10-12 13:47:40 -06:00
tangxifan 3aeea724de [Documentation] Update for new options in fpga-verilog 2020-10-12 12:36:24 -06:00
Laboratory for Nano Integrated Systems (LNIS) 5efe1ae77d
Merge pull request #106 from LNIS-Projects/dev 
Documentation update
 2020-10-10 23:16:37 -06:00
tangxifan ccaa697e5a [Documentation] Add links to technical features to examples 2020-10-10 22:40:37 -06:00
Andrew Lukefahr 00295a003f Docs: Updated note to enable VPR's GUI 2020-10-06 20:47:43 -04:00
tangxifan 800931c840 [Documentation] Add configuration protocol to technical highlights 2020-10-06 12:16:15 -06:00
tangxifan 56ab63d939 [Documentation] Fix format in table 2020-10-06 12:02:15 -06:00
tangxifan c8339fc473 [Documentation] Typo fix 2020-10-06 12:00:30 -06:00
tangxifan 113708c68f [Documentation] Reorganization the overview part by adding technical highlights 2020-10-06 11:56:10 -06:00
tangxifan 02e21d115b [Documentation] Update 3-rd party tool version requirements 2020-10-06 10:00:12 -06:00
tangxifan 67300af987 [Documentation] Update motivation with new set of figures 2020-09-29 16:52:16 -06:00
tangxifan 6817c045c2 [Documentation] Update tutorial about tooling 2020-09-29 16:24:52 -06:00
tangxifan 639d57016b [Documentation] Update documentation about the multi-region configuration 2020-09-29 15:55:42 -06:00
tangxifan 462886fb5f [Documentation] Update documentation for the multiple region support on configuration chain 2020-09-29 14:02:03 -06:00