tangxifan
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dcbd6a0614
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[Architecture] Add lib name to TGATE to test compatibility
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2020-09-25 21:08:12 -06:00 |
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tangxifan
|
1b4e449179
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[OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol
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2020-09-25 21:05:20 -06:00 |
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tangxifan
|
6bea712db0
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[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
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2020-09-25 14:54:51 -06:00 |
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tangxifan
|
019208ec0f
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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tangxifan
|
20d6b2bf84
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[Architecture] Remove out-of-date Verilog testbench
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2020-09-24 21:14:13 -06:00 |
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tangxifan
|
00bf775971
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[Architecture] Bug fix for adder renaming
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2020-09-24 20:54:18 -06:00 |
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tangxifan
|
0a53a719bd
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[Architecture] Bug fix due to adder renaming
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2020-09-24 20:42:24 -06:00 |
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tangxifan
|
e4bfa2ef51
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[Architecture] Update external bitstream file
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2020-09-24 20:16:50 -06:00 |
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tangxifan
|
bd0f0144a0
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[Architecture] Rename AIB architecture for the new cell naming
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2020-09-24 20:14:16 -06:00 |
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tangxifan
|
8edfc79f53
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[Architecture] Rename AIB cell
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2020-09-24 20:11:21 -06:00 |
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tangxifan
|
4ada793c84
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[Architecture] Adapt openfpga architecture to follow the renamed adder cell
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2020-09-24 20:09:29 -06:00 |
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tangxifan
|
53187044e6
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[Architecture] Rename adder cell
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2020-09-24 20:07:57 -06:00 |
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tangxifan
|
4a0a448171
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[Architecture] Rename openfpga architecture for the I/O cell
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2020-09-24 19:56:01 -06:00 |
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tangxifan
|
e0f9547f5b
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[Architecture] Rework the i/o cell Verilog HDL
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2020-09-24 19:53:54 -06:00 |
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tangxifan
|
eb5fd1f44e
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[Architecture] Bug fix for architectures using scan-chain DFF cell
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2020-09-24 18:37:25 -06:00 |
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tangxifan
|
60a14ccbd2
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[Architecture] Bug fix in architectures that use BRAM
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2020-09-24 18:20:55 -06:00 |
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tangxifan
|
d51efd397f
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[Architecture] Bug fix for architectures using DFF cells
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2020-09-24 18:02:42 -06:00 |
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tangxifan
|
3ade6d6ff5
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[Architecture] Bug fix for dff that are used in data path
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2020-09-24 17:53:30 -06:00 |
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tangxifan
|
3e7c88eac8
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[Architecture] Bug fix in Verilog netlist for scan-chain DFF
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2020-09-24 17:41:03 -06:00 |
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tangxifan
|
7494556316
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[Architecture] Bug fix for scan-chain FF cell
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2020-09-24 17:38:16 -06:00 |
|
tangxifan
|
54b3f244d3
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[Architecture] Remove obsolete Verilog netlists
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2020-09-24 17:35:02 -06:00 |
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tangxifan
|
49d6863641
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[Architecture] Bug fix for scan-chain FF cell renaming
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2020-09-24 17:33:14 -06:00 |
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tangxifan
|
0a5369f919
|
[Architecture] Adapt all the architecture files to use standard DFF cell
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2020-09-24 17:26:48 -06:00 |
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tangxifan
|
a30255b2a4
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[Regression Test] Deploy new test cases to CI
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2020-09-24 17:04:43 -06:00 |
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tangxifan
|
19dd3778d9
|
[Architecture] Add test case for memory bank to use both reset and set
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2020-09-24 17:04:24 -06:00 |
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tangxifan
|
335f5b78c1
|
[Regression Test] Add test case to use both set and reset for configuration frame
|
2020-09-24 17:02:28 -06:00 |
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tangxifan
|
2d81ff9012
|
[Regression test] Add configuration chain test case where both set and reset are used
|
2020-09-24 16:59:52 -06:00 |
|
tangxifan
|
fc154b8560
|
[Architecture] Bug fix due to switching CCFF cell
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2020-09-24 16:45:56 -06:00 |
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tangxifan
|
4d94fcb298
|
[Regression Test] Bug fix in calling test cases
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2020-09-24 16:38:34 -06:00 |
|
tangxifan
|
8468f25b23
|
[OpenFPGA Tool] Bug fix in the smart fast configuration strategy
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2020-09-24 16:31:55 -06:00 |
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tangxifan
|
79875d5a91
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[Architecture] Bug fix in the configuration chain arch using both reset and set
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2020-09-24 15:27:26 -06:00 |
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tangxifan
|
9cb67e6097
|
[Architecture] Now all the configuration chain architecture use the DFFR cell by default
|
2020-09-24 15:19:37 -06:00 |
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tangxifan
|
81965e75f6
|
[Architecture] Bug fix in DFF Verilog HDL
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2020-09-24 14:53:21 -06:00 |
|
tangxifan
|
3b42fe94d6
|
[Architecture] Update external bitstream file
|
2020-09-24 14:41:44 -06:00 |
|
tangxifan
|
08838c4957
|
[Regression Test] Deploy new configuration chain test cases to CI
|
2020-09-24 14:36:39 -06:00 |
|
tangxifan
|
7fbccdd102
|
[Regression Tests] Add test cases for configuration chain using different DFF cells
|
2020-09-24 14:34:12 -06:00 |
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tangxifan
|
178afb3c7f
|
[Architecture] Add configuration chain architectures using different DFF cells
|
2020-09-24 14:23:27 -06:00 |
|
tangxifan
|
98d88dc686
|
[Architecture] Bug fix for vanilla memory organization
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2020-09-24 14:13:48 -06:00 |
|
tangxifan
|
efad0402c2
|
[Regression Test] Bug fix for CI errors
|
2020-09-24 13:55:41 -06:00 |
|
tangxifan
|
e7906899dd
|
[Regression test] Bug fix for fast configuration frame. Now should use a latch with reset
|
2020-09-24 13:53:12 -06:00 |
|
tangxifan
|
e832d806c7
|
[Architecture] Add DFF Verilog netlist using standard naming convention
|
2020-09-24 13:50:59 -06:00 |
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tangxifan
|
1b13e8ecb1
|
[Architecture] Bug fix in the SRAM Verilog
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2020-09-24 12:26:13 -06:00 |
|
tangxifan
|
9d9cf6ee71
|
[Regression Test] Deploy new tests to CI
|
2020-09-24 12:20:18 -06:00 |
|
tangxifan
|
ffd1a72d22
|
[Architecture] Add regression tests for the frame-based configuration using reset and set signals
|
2020-09-24 12:18:26 -06:00 |
|
tangxifan
|
539bb617f9
|
[Architecture] Add reset test case for frame based configuration
|
2020-09-24 12:17:18 -06:00 |
|
tangxifan
|
2add0406a7
|
[Architecture] Update architecture files for new latch naming
|
2020-09-24 12:14:03 -06:00 |
|
tangxifan
|
fde15c4f88
|
[Regression Test] Add test for fast memory bank configuration using set signals
|
2020-09-24 12:13:35 -06:00 |
|
tangxifan
|
7238a2be03
|
[Architecture] Merge latch Verilog HDL to a unique file
|
2020-09-24 11:02:01 -06:00 |
|
tangxifan
|
48083d2276
|
[Regression Test] Adapt fast memory bank test case
|
2020-09-24 10:32:03 -06:00 |
|
tangxifan
|
83971bba41
|
[Architecture] Update cell ports for native SRAM cell
|
2020-09-24 10:31:31 -06:00 |