tangxifan
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dc68c52d0a
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[Test] Now use a light architecture to speed up the test case runtime
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2020-10-12 12:53:34 -06:00 |
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tangxifan
|
e59377a3ec
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[Flow] bug fix in the sample script for fabric netlist customization
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2020-10-12 12:52:01 -06:00 |
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tangxifan
|
8941e38613
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[Test] Enable verification in the new test case
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2020-10-12 12:50:08 -06:00 |
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tangxifan
|
9e1fd300dc
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[Test] Add test case for customized location of fabric netlists
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2020-10-12 12:47:58 -06:00 |
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tangxifan
|
e510e79c12
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[Flow] Add openfpga shell example script to use fabric netlist option
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2020-10-12 12:42:43 -06:00 |
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tangxifan
|
3aeea724de
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[Documentation] Update for new options in fpga-verilog
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2020-10-12 12:36:24 -06:00 |
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tangxifan
|
1ef0898f41
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[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
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2020-10-12 12:31:51 -06:00 |
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tangxifan
|
ccaa697e5a
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[Documentation] Add links to technical features to examples
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2020-10-10 22:40:37 -06:00 |
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tangxifan
|
ea3a1b785c
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[Documentation] Fix the path to OpenFPGA logo in the README
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2020-10-10 21:44:18 -06:00 |
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tangxifan
|
b8c20959b6
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[Regression test] Add new test case to CI
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2020-10-10 20:29:00 -06:00 |
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tangxifan
|
82e7b159ce
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[Regression test] Add test case for fracturable LUT using AND gate to switch modes
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2020-10-10 20:26:41 -06:00 |
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tangxifan
|
d0014878d5
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[Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes
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2020-10-10 20:24:57 -06:00 |
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tangxifan
|
721bcce373
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[Tool] Change analysis SDC file name to track netlist name
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2020-10-10 17:43:35 -06:00 |
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tangxifan
|
800931c840
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[Documentation] Add configuration protocol to technical highlights
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2020-10-06 12:16:15 -06:00 |
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tangxifan
|
56ab63d939
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[Documentation] Fix format in table
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2020-10-06 12:02:15 -06:00 |
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tangxifan
|
c8339fc473
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[Documentation] Typo fix
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2020-10-06 12:00:30 -06:00 |
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tangxifan
|
113708c68f
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[Documentation] Reorganization the overview part by adding technical highlights
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2020-10-06 11:56:10 -06:00 |
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tangxifan
|
02e21d115b
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[Documentation] Update 3-rd party tool version requirements
|
2020-10-06 10:00:12 -06:00 |
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tangxifan
|
67300af987
|
[Documentation] Update motivation with new set of figures
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2020-09-29 16:52:16 -06:00 |
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tangxifan
|
6817c045c2
|
[Documentation] Update tutorial about tooling
|
2020-09-29 16:24:52 -06:00 |
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tangxifan
|
639d57016b
|
[Documentation] Update documentation about the multi-region configuration
|
2020-09-29 15:55:42 -06:00 |
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tangxifan
|
d4d02ab16a
|
[Regression Test] Move fabric key tests to basic tests
|
2020-09-29 14:22:23 -06:00 |
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tangxifan
|
ff6570df9d
|
[Regression Test] Bug fix for fabric key test cases using multiple regions and deploy tests to CI
|
2020-09-29 14:19:40 -06:00 |
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tangxifan
|
4f00d310d3
|
[Architecture] Add example fabric key using multiple regions
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2020-09-29 14:14:50 -06:00 |
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tangxifan
|
02ea639959
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[Regression Test] Add test for fabric key based on multiple region
|
2020-09-29 14:13:38 -06:00 |
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tangxifan
|
462886fb5f
|
[Documentation] Update documentation for the multiple region support on configuration chain
|
2020-09-29 14:02:03 -06:00 |
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tangxifan
|
6e8ebd7979
|
[Regression Tests] Deploy multi-region test cases to CI
|
2020-09-29 13:57:31 -06:00 |
|
tangxifan
|
a0d1d68402
|
[Regression Test] Add regression tests for smart fast configuration chain using multiple regions
|
2020-09-29 13:53:41 -06:00 |
|
tangxifan
|
d5c7411399
|
[Architecture] Add more architecture to test fast configuration support on the multi-region configuration chain
|
2020-09-29 13:50:31 -06:00 |
|
tangxifan
|
5be5835b71
|
[Regression Test] Add multiple region configuration chain test case
|
2020-09-29 13:48:39 -06:00 |
|
tangxifan
|
23449dc5c3
|
[Architecture] Add multiple region configuration chain architecture
|
2020-09-29 13:46:40 -06:00 |
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tangxifan
|
e0d7bcfa11
|
[Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols
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2020-09-29 12:49:32 -06:00 |
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tangxifan
|
e988e35f81
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[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
|
2020-09-29 12:22:10 -06:00 |
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tangxifan
|
180d72f3e5
|
[Tool] Add regions to fabric bitstream
|
2020-09-28 21:04:08 -06:00 |
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tangxifan
|
e179a58b15
|
[OpenFPGA Tool] Bug fix for long runtime
|
2020-09-28 20:42:18 -06:00 |
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tangxifan
|
47f3c79927
|
[OpenFPGA Tool] Bug fix in module manager due to configurable regions
|
2020-09-28 19:08:19 -06:00 |
|
tangxifan
|
f93d46a870
|
[OpenFPGA Tool] Add multiple configuration chain support in top module builder
|
2020-09-28 19:03:19 -06:00 |
|
tangxifan
|
552dddffd0
|
[OpenFPGA Tool] Support configurable regions in module manager
|
2020-09-28 18:13:07 -06:00 |
|
tangxifan
|
1e70825383
|
[OpenFPGA Tool] Add XML syntax for configurable regions
|
2020-09-28 13:51:43 -06:00 |
|
tangxifan
|
052b8b71c7
|
[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
|
2020-09-27 20:54:58 -06:00 |
|
tangxifan
|
491433fae2
|
[OpenFPGA Tool] Update XML parser for fabric regions
|
2020-09-27 20:41:01 -06:00 |
|
tangxifan
|
e09e5fa6c6
|
[Architecture] Update fabric key for region syntax
|
2020-09-27 20:40:37 -06:00 |
|
tangxifan
|
48b2bff0d9
|
[OpenFPGA Tool] Update fabric key data structure to support regions
|
2020-09-27 20:08:11 -06:00 |
|
tangxifan
|
bbdea4a46b
|
[Regression Test] Remove out-of-update sub modules
|
2020-09-27 19:23:13 -06:00 |
|
tangxifan
|
e95eacfbd9
|
Merge branch 'dev' into ganesh_dev
|
2020-09-27 17:01:57 -06:00 |
|
tangxifan
|
94047037c5
|
[OpenFPGA Tool] Streamline codes in openfpga arch parser
|
2020-09-27 14:33:14 -06:00 |
|
tangxifan
|
94a1324f05
|
[Documentation] Remove deprecated XML syntax
|
2020-09-26 14:31:57 -06:00 |
|
tangxifan
|
51d96244c6
|
[OpenFPGA Tool] Remove deprecated XML syntax
|
2020-09-26 14:30:57 -06:00 |
|
tangxifan
|
154f23b108
|
[OpenFPGA Tool] Add self-testing Verilog codes for configuration done signals in full testbenches
|
2020-09-26 11:54:06 -06:00 |
|
tangxifan
|
ffd926d686
|
[Architecture] Update external bitstream
|
2020-09-25 21:30:59 -06:00 |