AurelienUoU
|
345a081eff
|
Correct error of target to rewrite file in regression test
|
2019-06-07 17:37:56 -06:00 |
tangxifan
|
44ce0e8834
|
update gsb unique module detection and fix formal verification port direction
|
2019-06-07 17:18:38 -06:00 |
|
tangxifan
|
24d53390d8
|
clean up DeviceRRGSB internal data and member functions
|
2019-06-07 14:45:56 -06:00 |
|
tangxifan
|
c9f810ceb6
|
update rr_gsb to build connection blocks
|
2019-06-07 11:01:55 -06:00 |
|
tangxifan
|
472aff5acb
|
add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
|
2019-06-06 23:45:21 -06:00 |
|
tangxifan
|
ce9fc5696c
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rename rr_switch_block to rr_gsb, a generic block
|
2019-06-06 17:41:01 -06:00 |
|
tangxifan
|
8c1e7b799f
|
fixed critical bugs in Connection Block Unique Module detection
|
2019-06-06 16:31:50 -06:00 |
|
tangxifan
|
4f543c510c
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-06 12:50:03 -06:00 |
|
tangxifan
|
873e4d989f
|
fine-tuning Verilog format and node addition to rr_blocks
|
2019-06-06 12:48:41 -06:00 |
|
AurelienUoU
|
182d49da45
|
Update regression test scripts
|
2019-06-06 11:47:51 -06:00 |
|
tangxifan
|
c2de0eefb1
|
fix redundant comma in SB Verilog module
|
2019-06-06 09:15:05 -06:00 |
|
tangxifan
|
b9e1b1afc4
|
fix a critical bug in num_reserved_sram_ports
|
2019-06-05 17:31:01 -06:00 |
|
tangxifan
|
aaf8d23971
|
fix critical bugs in routing submodules
|
2019-06-05 16:43:18 -06:00 |
|
tangxifan
|
01e075377d
|
fix typo in Verilog generation
|
2019-06-05 15:30:34 -06:00 |
|
tangxifan
|
21d0cb52bc
|
Merge remote-tracking branch 'origin' into tileable_sb
|
2019-06-05 13:31:49 -06:00 |
|
tangxifan
|
24ca3104b0
|
fix minor bugs in Switch Block submodules
|
2019-06-05 13:30:55 -06:00 |
|
tangxifan
|
0f87ae9886
|
support switch block submodule Verilog generation by segments
|
2019-06-05 12:56:05 -06:00 |
|
AurelienUoU
|
84fabbd43b
|
Fix sdc analysis bug related to virtual nodes + add the option in regression test
|
2019-06-05 12:10:28 -06:00 |
Baudouin Chauviere
|
d24488092d
|
Fix bug
|
2019-06-05 11:40:04 -06:00 |
|
tangxifan
|
c2d8fa00ba
|
add rr_block unique_side_module verilog generation
|
2019-06-04 17:47:40 -06:00 |
|
AurelienUoU
|
fcc10d8acf
|
Correct fpga_flow/arch/template files
|
2019-06-04 16:45:04 -06:00 |
|
AurelienUoU
|
a2f6ded2a2
|
Add path modification in file changing a keyword into OpenFPGA full path
|
2019-06-04 15:21:15 -06:00 |
|
tangxifan
|
98b82c17be
|
bug fixing for clear RRSwitchBlock
|
2019-06-04 14:02:49 -06:00 |
|
tangxifan
|
2c6780ab92
|
add side mirror detection for RRSwitchBlock
|
2019-06-04 13:01:22 -06:00 |
|
AurelienUoU
|
eb72cb201c
|
Use debug cmake build type to avoid building error
|
2019-06-03 15:34:26 -06:00 |
|
AurelienUoU
|
6974a4618f
|
Test gcc6 cmake3.13
|
2019-06-03 14:53:52 -06:00 |
|
AurelienUoU
|
f51aa41c23
|
Correct gcc instantiation
|
2019-06-03 14:13:22 -06:00 |
|
AurelienUoU
|
c87c349c75
|
Test gcc6/cmake3.5
|
2019-06-03 13:58:00 -06:00 |
|
AurelienUoU
|
f4b8c3cf25
|
Try another combination cmake/gcc
|
2019-06-03 13:45:34 -06:00 |
|
AurelienUoU
|
ab9834798a
|
Test if travis issue is the same as spotted on VM
|
2019-06-03 12:01:37 -06:00 |
|
AurelienUoU
|
8a5ff37262
|
Verify cmake version called to build
|
2019-06-03 11:16:39 -06:00 |
|
AurelienUoU
|
813470d459
|
Test Cmake fix
|
2019-06-03 10:31:44 -06:00 |
|
AurelienUoU
|
4523bd21e9
|
Update version of cmake causing trouble
|
2019-06-03 10:21:24 -06:00 |
|
AurelienUoU
|
7368e6d7e4
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-31 11:01:07 -06:00 |
|
AurelienUoU
|
737300eb54
|
Fix regression test
|
2019-05-31 11:00:30 -06:00 |
|
Baudouin Chauviere
|
1932d00309
|
Correction of the SDC to remove global clocks
|
2019-05-30 15:04:21 -06:00 |
|
AurelienUoU
|
ba05a08ef0
|
Path correction in tech debugging + correction of yosys rewrite file in fpga_flow
|
2019-05-30 09:52:19 -06:00 |
|
AurelienUoU
|
0e820d38ea
|
Speedup the install on travis
|
2019-05-29 16:53:35 -06:00 |
|
AurelienUoU
|
46fa1197b0
|
Test reading tech file
|
2019-05-29 16:43:56 -06:00 |
|
AurelienUoU
|
74ee6bad7f
|
Update spice path in architecture
|
2019-05-29 10:08:58 -06:00 |
|
tangxifan
|
5b15a746d3
|
add num_driver_nodes to Switch Block XML writter
|
2019-05-28 20:52:33 -06:00 |
|
tangxifan
|
5ed076dfb4
|
fixed a critical bug in rotating
|
2019-05-28 17:55:09 -06:00 |
|
tangxifan
|
9cc5518d5a
|
keep adding segment information for SB XML outputter
|
2019-05-28 15:59:55 -06:00 |
|
tangxifan
|
e7e18eb4c1
|
Add more information in SB XML outputter
|
2019-05-28 15:56:41 -06:00 |
|
tangxifan
|
ca402f87e5
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-28 15:19:48 -06:00 |
|
tangxifan
|
ca363da30c
|
add options to specify output directory of SB XML
|
2019-05-28 15:19:10 -06:00 |
|
AurelienUoU
|
4ef25a7550
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-28 15:03:40 -06:00 |
|
AurelienUoU
|
f934f6f0a3
|
Debug step
|
2019-05-28 15:01:16 -06:00 |
|
tangxifan
|
6b51b42ee7
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-28 14:53:44 -06:00 |
|
tangxifan
|
af91fca1e0
|
add rr_blocks XML writer to help debugging Switch Block Rotation
|
2019-05-28 14:52:44 -06:00 |