tangxifan
|
8edd85c9fc
|
keep fixing bugs in verilog SDC generator for tileable CBs
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2019-06-26 22:58:52 -06:00 |
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tangxifan
|
711e369fe7
|
fixing bugs in the SDC generator and report_timing
|
2019-06-26 18:09:09 -06:00 |
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tangxifan
|
0fe54d87d5
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fixed a bug in SDC generator for constraining SBs in tileable arch
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2019-06-26 17:06:14 -06:00 |
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tangxifan
|
7d85eb544d
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start fixing bugs for SDC generator when using tileable arch
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2019-06-26 16:48:17 -06:00 |
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tangxifan
|
f5920c7422
|
fix bugs in ptc_num using for SB
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2019-06-26 16:21:02 -06:00 |
|
tangxifan
|
3d8200e217
|
critical bug fixed in bitstream generator for compact routing hierarchy
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2019-06-26 15:51:11 -06:00 |
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tangxifan
|
d2ed82d14d
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Merge branch 'tileable_routing' into multimode_clb
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2019-06-26 15:00:39 -06:00 |
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tangxifan
|
57616361c2
|
fixed critical bugs in cb configuration port indices
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2019-06-26 14:58:52 -06:00 |
Baudouin Chauviere
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d2bd2be76b
|
Warnings correction in the make sequence
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2019-06-26 14:33:12 -06:00 |
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tangxifan
|
42f85004b6
|
fix bugs in finding the ending SB of a rr_node
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2019-06-26 14:13:41 -06:00 |
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tangxifan
|
9b6a4b39bb
|
Merge branch 'tileable_routing' into multimode_clb
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2019-06-26 11:36:08 -06:00 |
|
tangxifan
|
c879e7f6c5
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fixed a critical bug when instanciating Connection blocks
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2019-06-26 11:33:02 -06:00 |
|
Baudouin Chauviere
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b7c2954b91
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-26 10:51:55 -06:00 |
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Baudouin Chauviere
|
8f21a3b177
|
Memory leakage correction
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2019-06-26 10:50:38 -06:00 |
|
tangxifan
|
d50fb7ee19
|
fixed the bug in determine passing wires for rr_gsb
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2019-06-26 10:50:23 -06:00 |
AurelienUoU
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ec504049ef
|
Update Testbenches to increase accuracy + commented compact routing option until debug
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2019-06-26 10:01:12 -06:00 |
|
Baudouin Chauviere
|
56557b94e7
|
Bug Fix
|
2019-06-26 08:53:46 -06:00 |
|
Baudouin Chauviere
|
bb250ddef9
|
Bug fix in cpp
|
2019-06-25 16:47:10 -06:00 |
|
Baudouin Chauviere
|
332ce17f03
|
Division between horizontal and vertical analysis
|
2019-06-25 13:44:41 -06:00 |
|
Baudouin Chauviere
|
be25b6dd66
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-20 14:11:03 -06:00 |
|
Baudouin Chauviere
|
3bd6c40a10
|
Report timing modified to have only one liners
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2019-06-20 14:10:39 -06:00 |
|
AurelienUoU
|
a7502bb43b
|
Avoid configuration bits for module wihch don't require them
|
2019-06-20 09:40:41 -06:00 |
|
Baudouin Chauviere
|
57a4ad1f99
|
Break memories even in the clb sdc
|
2019-06-16 14:27:29 -06:00 |
|
tangxifan
|
4d2a3680be
|
support bus explicit port mapping to standard cells (for BRAMs)
|
2019-06-14 11:09:15 -06:00 |
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tangxifan
|
0902d1e75a
|
c++ string is not working, use char which is stable
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2019-06-13 18:38:46 -06:00 |
|
tangxifan
|
af1628abfe
|
use bus port for primitives in Verilog generator
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2019-06-13 16:26:58 -06:00 |
|
tangxifan
|
dddbbac85c
|
merge from multimode_clb bug fixing
|
2019-06-13 15:59:34 -06:00 |
|
tangxifan
|
43128ad3f0
|
fix a bug in formal verification port for memory bank configuration circuits
|
2019-06-13 15:33:13 -06:00 |
|
tangxifan
|
44d21ebb90
|
fixed a bug in Verilog generator supporting SRAM5T
|
2019-06-13 14:42:39 -06:00 |
|
tangxifan
|
1776ae3ec8
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
|
tangxifan
|
009e5244d3
|
minor fix on the port direction of configuration peripherals for memory decoders
|
2019-06-10 15:39:35 -06:00 |
|
tangxifan
|
f43955037c
|
remove input port requirements for SRAM circuit module
|
2019-06-10 15:29:44 -06:00 |
|
tangxifan
|
e4f70771a2
|
updated SDC generator to embrace the RRGSB data structure
|
2019-06-10 14:47:27 -06:00 |
|
tangxifan
|
8a8f4153ce
|
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
|
2019-06-10 12:50:10 -06:00 |
|
tangxifan
|
e31407f693
|
start cleaning up SDC generator with new RRGSB data structure
|
2019-06-10 10:57:26 -06:00 |
|
tangxifan
|
17bc7fc296
|
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
|
2019-06-08 20:11:22 -06:00 |
|
tangxifan
|
8c5ec4572d
|
revert string to sprintf
|
2019-06-07 20:20:41 -06:00 |
|
tangxifan
|
0f1ed19ad0
|
Revert to the use of sprintf instead std::string. Have no idea why string is not working
|
2019-06-07 18:54:57 -06:00 |
|
tangxifan
|
44ce0e8834
|
update gsb unique module detection and fix formal verification port direction
|
2019-06-07 17:18:38 -06:00 |
|
tangxifan
|
24d53390d8
|
clean up DeviceRRGSB internal data and member functions
|
2019-06-07 14:45:56 -06:00 |
|
tangxifan
|
472aff5acb
|
add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
|
2019-06-06 23:45:21 -06:00 |
|
tangxifan
|
ce9fc5696c
|
rename rr_switch_block to rr_gsb, a generic block
|
2019-06-06 17:41:01 -06:00 |
|
tangxifan
|
873e4d989f
|
fine-tuning Verilog format and node addition to rr_blocks
|
2019-06-06 12:48:41 -06:00 |
|
tangxifan
|
c2de0eefb1
|
fix redundant comma in SB Verilog module
|
2019-06-06 09:15:05 -06:00 |
|
tangxifan
|
b9e1b1afc4
|
fix a critical bug in num_reserved_sram_ports
|
2019-06-05 17:31:01 -06:00 |
|
tangxifan
|
aaf8d23971
|
fix critical bugs in routing submodules
|
2019-06-05 16:43:18 -06:00 |
|
tangxifan
|
01e075377d
|
fix typo in Verilog generation
|
2019-06-05 15:30:34 -06:00 |
|
tangxifan
|
21d0cb52bc
|
Merge remote-tracking branch 'origin' into tileable_sb
|
2019-06-05 13:31:49 -06:00 |
|
tangxifan
|
24ca3104b0
|
fix minor bugs in Switch Block submodules
|
2019-06-05 13:30:55 -06:00 |
|
tangxifan
|
0f87ae9886
|
support switch block submodule Verilog generation by segments
|
2019-06-05 12:56:05 -06:00 |