6ce0fe4ef2
doc update for FPGA-bitstream to better motivate the different types of bitstream
2020-04-01 12:57:28 -06:00
fd8248d9dd
update documentation: the addon syntax on VPR and configuration protocols
2020-04-01 12:35:52 -06:00
63306ce3a0
add comments to explain the memory organization in the top-level module
2020-04-01 11:05:30 -06:00
5d12f499f0
hotfix on undriven pins on the connection blocks
2020-03-29 16:26:23 -06:00
07e1979498
add architecture examples on wide memory blocks (width=2). tileable routing is working
2020-03-28 15:41:26 -06:00
ff9cc50527
relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
2020-03-27 20:09:50 -06:00
e601a648cc
relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
2020-03-27 19:07:34 -06:00
34a1b61ecb
add an example FPGA architecture with AIB interface at the right side of I/Os
2020-03-27 18:45:27 -06:00
4bf0a63ae6
bug fixed for multiple io types defined in FPGA architectures
2020-03-27 16:32:15 -06:00
7c9c2451f2
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
2020-03-27 16:03:42 -06:00
b09b051249
add all the test cases considering tileable, carry chain, direct connection and memory blocks
2020-03-27 13:58:35 -06:00
78964ce71c
update documentation on the through channel
2020-03-27 11:34:39 -06:00
e47a0a4422
add through channel architecture example
2020-03-27 11:32:44 -06:00
5ce078fe60
minor fix on rr_graph.clear()
2020-03-27 11:26:14 -06:00
91a618466d
bug fixing for rr_graph.clear() function
2020-03-27 10:52:48 -06:00
3b3c39454b
update print_route() in VPR to show correct track_id when tileable routing is used
2020-03-25 17:55:28 -06:00
b4221e94bb
add documentation on the tileable routing and thru channel support
2020-03-25 16:52:42 -06:00
cb6afea07c
update documentation on a new option in FPGA-SDC to constrain zero-delay paths
2020-03-25 16:00:25 -06:00
329b0a9cf1
add options to enable SDC constraints on zero-delay paths
2020-03-25 15:55:30 -06:00
3a74fb7a04
update documentation for the new options
2020-03-25 15:23:21 -06:00
4a0128f240
minor fix on the SDC format
2020-03-25 14:46:31 -06:00
62b6de8437
update the SDC of VPR7+OpenFPGA to be even with VPR8+OpenFPGA
2020-03-25 14:44:42 -06:00
c2e5d6b8e2
add options to dsiable SDC for non-clock global ports
2020-03-25 14:38:13 -06:00
787dc8ce83
added ASCII OpenFPGA logo in shell interface
2020-03-25 11:16:04 -06:00
b6bdf78d95
bug fixed for heterogeneous block instances in top module
2020-03-24 17:39:26 -06:00
610c71671f
experimentally developing through channels inside multi-width and multi-height grids.
...
Still debugging.
2020-03-24 16:47:45 -06:00
8a996ceae5
bug fixed in tileable routing when heterogeneous blocks are considered;
...
VPR have special rules in checking the coordinates of SOURCE and SINK nodes,
which is very different from the OPIN and IPIN nodes
Show respect to it here.
2020-03-24 13:02:35 -06:00
08b46af7be
add micro architecture for heterogeneous FPGA with single-mode DPRAM
2020-03-24 12:20:51 -06:00
7e3a8e5794
typo fixed in fpga-bitstream documentation
2020-03-22 16:27:12 -06:00
75dfe6a045
update documentation for write_gsb_to_xml functionality
2020-03-22 16:21:35 -06:00
9e4e12aae9
fixed echo message in the compression rate of gsb uniquifying
2020-03-22 16:13:04 -06:00
ff474d87de
fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs
2020-03-22 16:11:00 -06:00
fdf6a6bd3e
use chan_node_in_edges from rr_gsb in XML writer
2020-03-22 15:48:11 -06:00
3958ac2494
fix bugs in flow manager on default compress routing problems
2020-03-22 15:26:15 -06:00
fc6abc13fd
add physical tile utils to identify pins that have Fc=0
2020-03-21 21:02:47 -06:00
7b9384f3b2
add write_gsb command to shell interface
2020-03-21 19:40:26 -06:00
637be076dc
adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working
2020-03-21 18:49:20 -06:00
9a518e8bb6
bug fixed for tileable rr_graph builder for more 4x4 fabrics
2020-03-21 18:07:00 -06:00
63c4669dbb
fixed bug in the fast look-up for tileable rr_graph
2020-03-21 17:36:08 -06:00
c0e8d98c6f
bug fixed in tile direct builder
2020-03-21 12:43:56 -06:00
8f35f191eb
use the formalized function in FPGA-SDC to identify direct connection
2020-03-21 11:42:00 -06:00
28123b8052
remove the direct connected IPIN/OPIN from RR GSB builder
2020-03-21 11:38:39 -06:00
2ff2d65e58
start debugging tileable routing using larger array size. Bug spotted in finding chan nodes
2020-03-20 22:12:23 -06:00
682b667a3c
minor bug fix for direct connection in FPGA-SDC
2020-03-20 21:44:01 -06:00
05ec86430a
temp fix for direct connections. Should notify VPR team about this issue: delayless switch is used in direct connection but it is considered as configurable....which is actually NOT!
2020-03-20 17:56:03 -06:00
3c37b33f17
critical bug fixed in edge sorting for rr_gsb
2020-03-20 17:45:50 -06:00
060c1a41d9
critical bug fixed for tileable routing: delayless and wire2ipin switch was reverted
2020-03-20 17:23:19 -06:00
2c0c5a061b
spot a bug in assigning rr_switch in tileable routing
2020-03-20 16:53:43 -06:00
708fda9606
fixed a bug in using tileable routing when directlist is enabled
2020-03-20 16:38:58 -06:00
c5049a1ec8
keep debugging tile direct connections
2020-03-20 15:10:00 -06:00
Xifan Tang