tangxifan
|
b42541d84e
|
[Flow] Support multiple iterations in rewriting yosys scripts
|
2021-03-10 14:10:35 -07:00 |
|
tangxifan
|
035043d0d8
|
[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr
|
2021-03-10 13:36:11 -07:00 |
|
tangxifan
|
5d46537b5b
|
[Script] Allow users to specify custom post-synthesis verilog for simulation
|
2021-03-10 11:45:55 -07:00 |
|
tangxifan
|
aafd87c3f9
|
[Flow] Update flow-run to support custom yosys rewrite scripts
|
2021-03-10 11:36:29 -07:00 |
|
tangxifan
|
131643dcc0
|
[Flow] Bug fix for yosys rewrite function in openfpga flow-run script
|
2021-03-08 21:08:55 -07:00 |
ganeshgore
|
b860722893
|
Fixed parameter ys_rewrite_params name bug
|
2021-03-08 10:34:39 -07:00 |
|
ganeshgore
|
52de55e7eb
|
Merge branch 'master' into ganesh_dev
|
2021-03-08 10:15:06 -07:00 |
|
Ganesh Gore
|
7a35811430
|
[Flow] Yosys rewrite support
|
2021-03-08 00:35:47 -07:00 |
|
Ganesh Gore
|
67cd9a69b7
|
[Flow] Extended yosys variable subtitution
|
2021-03-08 00:21:07 -07:00 |
Lalit Sharma
|
6a1ce01084
|
Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
|
2021-03-07 22:02:11 -08:00 |
|
Lalit Sharma
|
0cbad747a1
|
Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
|
2021-03-04 01:10:47 -08:00 |
|
Lalit Sharma
|
817729ac86
|
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
|
2021-03-01 22:31:15 -08:00 |
|
tangxifan
|
d85d6e964e
|
Merge pull request #227 from watcag/master
Standard-cell flow
|
2021-02-17 10:11:34 -07:00 |
|
tangxifan
|
a819375f69
|
[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
|
2021-02-16 16:53:13 -07:00 |
Tarachand Pagarani
|
3a587f663a
|
copy yosys output file in case power analysis setting is off
|
2021-02-15 02:36:02 -08:00 |
Nachiket Kapre
|
b4185f7e8c
|
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA
|
2021-02-08 21:11:30 -05:00 |
|
Nachiket Kapre
|
2344cdcabc
|
merge
|
2021-02-08 21:11:28 -05:00 |
|
tangxifan
|
1ce94040da
|
Merge pull request #221 from lnis-uofu/flow_dev
[Flow] Support multi-user environment for running task
|
2021-02-08 12:43:57 -07:00 |
|
Ganesh Gore
|
ede5f8ed58
|
[Flow] Support multi-user enviroment for running task
|
2021-02-07 22:11:04 -07:00 |
|
Ganesh Gore
|
6cdc31f073
|
[Flow] ACE is optional duign flow script
|
2021-02-03 19:07:48 -07:00 |
|
Ganesh Gore
|
df4a397470
|
[Cleanup] Removed deadcode
|
2021-02-03 10:35:14 -07:00 |
|
Ganesh Gore
|
0b82b6439b
|
[Regression] Upgraded runtime enviroment to python3.8
|
2021-01-26 16:40:45 -07:00 |
|
ganeshgore
|
289d9d2169
|
[Bugfix] Honors yosys_tmpl parameter in flow script
|
2020-12-03 12:24:24 -07:00 |
|
ganeshgore
|
59bd7d0f18
|
[Flow] Changed substitute to safe_sustitute option
|
2020-11-25 22:09:36 -07:00 |
|
ganeshgore
|
fefba0db59
|
Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
|
2020-11-25 17:29:53 -07:00 |
|
ganeshgore
|
1554f583b7
|
[Flow] Now support explicit variable file for task
|
2020-11-25 17:22:41 -07:00 |
|
tangxifan
|
521accdc88
|
Merge pull request #104 from lukefahr/disp_fix
FLOW: fixed display flag
|
2020-10-07 09:54:06 -06:00 |
|
tangxifan
|
7b12c28e4f
|
Merge pull request #102 from lukefahr/blif_bug
Fixed blif formatting bug
|
2020-10-06 20:05:02 -06:00 |
Andrew Lukefahr
|
33bbe0ec48
|
FLOW: fixed display flag
|
2020-10-06 20:52:28 -04:00 |
|
Andrew Lukefahr
|
d68427e47b
|
Fixed blif formatting bug
|
2020-10-06 20:46:50 -04:00 |
|
Andrew Lukefahr
|
2d92a1f1af
|
Edits to enable basic run_fpga_flow.py
|
2020-10-02 10:18:10 -04:00 |
|
tangxifan
|
dbd93e429d
|
now pro_blif.pl can accept customized clock name
|
2020-08-19 09:43:44 -06:00 |
|
ganeshgore
|
747c062f86
|
BugFix : Flow script accepts extra OpenFPGA arguments
|
2020-07-27 18:10:43 -06:00 |
|
ganeshgore
|
45af056304
|
TASK_NAME and TASK_DIR variables are avaialble in config file now
|
2020-07-27 14:14:57 -06:00 |
|
ganeshgore
|
0e46e0d857
|
Updated task.conf format to have transparent shell variables
|
2020-07-27 14:08:58 -06:00 |
|
ganeshgore
|
3b6cd885f3
|
BugFix: Fixed yosys_vpr with openFPGA_Shell
|
2020-07-22 11:57:04 -06:00 |
|
tangxifan
|
4f8260a7ba
|
remove obselete codes and update regression tests
|
2020-07-04 17:31:34 -06:00 |
|
ganeshgore
|
41585436c8
|
Added external_fabric_key_file key
|
2020-06-12 15:37:12 -06:00 |
|
ganeshgore
|
c1b73efa62
|
Added support for simulation setting file in the task flow
|
2020-06-10 23:12:30 -06:00 |
|
ganeshgore
|
a3103f6afe
|
BugFix : Relative path for refrence benchmark fixed
|
2020-04-25 20:16:17 -06:00 |
|
ganeshgore
|
9d1b3d6865
|
Fixed modelsim include references
|
2020-04-24 21:53:57 -06:00 |
|
ganeshgore
|
689c4a3e19
|
BugFix: The filename in the previous commit
|
2020-04-15 12:44:22 -06:00 |
|
ganeshgore
|
7f37bf1441
|
Added formal verification support to fpga_flow script
|
2020-04-15 12:24:51 -06:00 |
|
ganeshgore
|
f6b3c5854a
|
Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
|
2020-04-11 16:45:22 -06:00 |
|
ganeshgore
|
8ea272dc2c
|
Patched the OpenFPGA shell execution bug
|
2020-04-08 21:28:14 -06:00 |
|
ganeshgore
|
583a4d8767
|
Fixed bug in openfpga_flow script
|
2020-04-08 12:04:08 -06:00 |
|
ganeshgore
|
ea4122a8a4
|
Updated openfpga_flow and task file to support sheel run
|
2020-04-06 00:34:36 -06:00 |
|
ganeshgore
|
d1d3446568
|
backedup partial upgrade for fpga_flow script
|
2020-04-05 11:36:24 -06:00 |
|
ganeshgore
|
46bb5ef9d0
|
Added disp option in openfpga_flow, Default is --nodisp
|
2020-01-23 10:04:38 -07:00 |
|
ganeshgore
|
f0bed1244c
|
Added blif file folding before VPR run
|
2020-01-09 16:50:34 -07:00 |