tangxifan
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44d21ebb90
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fixed a bug in Verilog generator supporting SRAM5T
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2019-06-13 14:42:39 -06:00 |
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tangxifan
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5ae4dec0af
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fix bugs in CMakeList on enable/disable VPR Graphics
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2019-06-12 22:48:00 -06:00 |
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tangxifan
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1d00e3665b
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start developing tileable_rr_graph_builder
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2019-06-11 16:50:40 -06:00 |
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tangxifan
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65b5454f3a
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start developing tileable_rr_graph_builder
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2019-06-11 16:49:10 -06:00 |
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tangxifan
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b359893852
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Merge branch 'multimode_clb' into tileable_routing
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2019-06-11 14:41:36 -06:00 |
AurelienUoU
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bf13c1f731
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Add a script to create a new file with correct path rather than overwrite the existing
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2019-06-11 14:28:58 -06:00 |
Ganesh Gore
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1da363f7f1
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Merge remote-tracking branch 'lnis_open_fpga/fpga_spice' into ganesh_dev
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2019-06-11 11:59:54 -06:00 |
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tangxifan
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7245917b9c
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fix a bug for iopad SPICE generation
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2019-06-11 11:43:56 -06:00 |
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Ganesh Gore
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1093e341a8
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Added additional architecure files
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2019-06-11 11:26:44 -06:00 |
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tangxifan
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1776ae3ec8
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add explicit port mapping for inverters of memory decoders
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2019-06-10 17:36:14 -06:00 |
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tangxifan
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8e3ad675e0
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use sstream for rr_block verilog writer
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2019-06-10 16:23:35 -06:00 |
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tangxifan
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009e5244d3
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minor fix on the port direction of configuration peripherals for memory decoders
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2019-06-10 15:39:35 -06:00 |
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tangxifan
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f43955037c
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remove input port requirements for SRAM circuit module
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2019-06-10 15:29:44 -06:00 |
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tangxifan
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e4f70771a2
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updated SDC generator to embrace the RRGSB data structure
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2019-06-10 14:47:27 -06:00 |
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tangxifan
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8a8f4153ce
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use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
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2019-06-10 12:50:10 -06:00 |
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tangxifan
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e31407f693
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start cleaning up SDC generator with new RRGSB data structure
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2019-06-10 10:57:26 -06:00 |
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tangxifan
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17bc7fc296
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update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
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2019-06-08 20:11:22 -06:00 |
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tangxifan
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3a7139ee65
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Merge branch 'tileable_sb' into multimode_clb
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2019-06-08 15:15:52 -06:00 |
|
Xifan Tang
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61e359efc5
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Enable an option to disable/enable graphics in VPR compilation
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2019-06-08 15:08:17 -06:00 |
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tangxifan
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90696def6d
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remove vpr Makefile
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2019-06-07 23:44:39 -06:00 |
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tangxifan
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d737c4ff46
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fix path in regression test! TODO: must keep a duplicated copy for template.xml
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2019-06-07 23:31:42 -06:00 |
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tangxifan
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3ad4a33751
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update travis to use gcc8 and disable graphics for vpr when compile in osx
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2019-06-07 22:38:21 -06:00 |
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tangxifan
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e8d52121c6
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try j16 for travis in linux
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2019-06-07 22:32:47 -06:00 |
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tangxifan
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1b02428c04
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change travis gcc and gxx setting
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2019-06-07 22:25:55 -06:00 |
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tangxifan
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f5b6ee6adf
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update travis configuration and clean up repository
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2019-06-07 22:19:11 -06:00 |
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tangxifan
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1f228dd42b
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Merge branch 'tileable_sb' into multimode_clb
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2019-06-07 20:23:32 -06:00 |
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tangxifan
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8c5ec4572d
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revert string to sprintf
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2019-06-07 20:20:41 -06:00 |
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tangxifan
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a55c577a61
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-07 18:56:32 -06:00 |
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tangxifan
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0f1ed19ad0
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Revert to the use of sprintf instead std::string. Have no idea why string is not working
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2019-06-07 18:54:57 -06:00 |
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AurelienUoU
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345a081eff
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Correct error of target to rewrite file in regression test
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2019-06-07 17:37:56 -06:00 |
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tangxifan
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44ce0e8834
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update gsb unique module detection and fix formal verification port direction
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2019-06-07 17:18:38 -06:00 |
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tangxifan
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24d53390d8
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clean up DeviceRRGSB internal data and member functions
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2019-06-07 14:45:56 -06:00 |
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tangxifan
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c9f810ceb6
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update rr_gsb to build connection blocks
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2019-06-07 11:01:55 -06:00 |
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tangxifan
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472aff5acb
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add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
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2019-06-06 23:45:21 -06:00 |
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tangxifan
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ce9fc5696c
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rename rr_switch_block to rr_gsb, a generic block
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2019-06-06 17:41:01 -06:00 |
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tangxifan
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8c1e7b799f
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fixed critical bugs in Connection Block Unique Module detection
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2019-06-06 16:31:50 -06:00 |
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tangxifan
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4f543c510c
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-06 12:50:03 -06:00 |
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tangxifan
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873e4d989f
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fine-tuning Verilog format and node addition to rr_blocks
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2019-06-06 12:48:41 -06:00 |
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AurelienUoU
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182d49da45
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Update regression test scripts
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2019-06-06 11:47:51 -06:00 |
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tangxifan
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c2de0eefb1
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fix redundant comma in SB Verilog module
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2019-06-06 09:15:05 -06:00 |
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tangxifan
|
b9e1b1afc4
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fix a critical bug in num_reserved_sram_ports
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2019-06-05 17:31:01 -06:00 |
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tangxifan
|
aaf8d23971
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fix critical bugs in routing submodules
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2019-06-05 16:43:18 -06:00 |
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tangxifan
|
01e075377d
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fix typo in Verilog generation
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2019-06-05 15:30:34 -06:00 |
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tangxifan
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21d0cb52bc
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Merge remote-tracking branch 'origin' into tileable_sb
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2019-06-05 13:31:49 -06:00 |
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tangxifan
|
24ca3104b0
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fix minor bugs in Switch Block submodules
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2019-06-05 13:30:55 -06:00 |
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tangxifan
|
0f87ae9886
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support switch block submodule Verilog generation by segments
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2019-06-05 12:56:05 -06:00 |
|
AurelienUoU
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84fabbd43b
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Fix sdc analysis bug related to virtual nodes + add the option in regression test
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2019-06-05 12:10:28 -06:00 |
Baudouin Chauviere
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d24488092d
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Fix bug
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2019-06-05 11:40:04 -06:00 |
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tangxifan
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c2d8fa00ba
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add rr_block unique_side_module verilog generation
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2019-06-04 17:47:40 -06:00 |
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AurelienUoU
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fcc10d8acf
|
Correct fpga_flow/arch/template files
|
2019-06-04 16:45:04 -06:00 |