tangxifan
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44d97ead86
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Merge branch 'master' into hetergeneous_arch
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2021-03-23 17:05:03 -06:00 |
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tangxifan
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b00b4f0f5f
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[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian
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2021-03-23 15:44:53 -06:00 |
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tangxifan
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d82ffe0cbf
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[Test] Deploy MAC_8 benchmark to regression test
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2021-03-23 15:36:28 -06:00 |
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tangxifan
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108c84a022
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[HDL] Add HDL for 8-bit single-mode multiplier
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2021-03-23 15:36:09 -06:00 |
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tangxifan
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145a80de43
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[Script] Add an openfpga shell script for heterogeneous fpga verification
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2021-03-23 15:35:34 -06:00 |
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tangxifan
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fdec72b5bc
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[Arch] Add an example architecture with 8-bit single-mode multiplier
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2021-03-23 15:35:06 -06:00 |
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tangxifan
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be03eafd66
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[Benchmark] Add a micro benchmark: 8-bit multiply and accumulate
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2021-03-23 15:33:37 -06:00 |
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tangxifan
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8c970a792a
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[Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier
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2021-03-23 15:33:00 -06:00 |
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tangxifan
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6b0409da60
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[Script] Add a template yosys script support only DSP mapping
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2021-03-23 15:32:10 -06:00 |
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tangxifan
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a4bbffd1aa
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[HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA
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2021-03-23 15:30:41 -06:00 |
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tangxifan
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fff16a01ab
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[Test] Update tolerance when checking VTR benchmark QoR
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2021-03-23 12:27:20 -06:00 |
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tangxifan
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781880ed93
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[Script] Add tolerance options to check qor script
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2021-03-23 12:26:33 -06:00 |
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tangxifan
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e3f8a6cf7a
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[Test] Deploy QoR check to VTR benchmark regression test
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2021-03-23 11:15:22 -06:00 |
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tangxifan
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351dec5935
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[Test] Add QoR csv file for vtr benchmarks
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2021-03-23 11:15:02 -06:00 |
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tangxifan
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23e7f7f1f5
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[Script] Update default list of result extraction for openfpga flow
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2021-03-23 11:06:42 -06:00 |
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tangxifan
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adfbd28a7a
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[Script] Add a simple QoR checker
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2021-03-23 11:06:16 -06:00 |
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tangxifan
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61eddb08de
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[Test] Update task configuration by commenting out high-runtime VTR benchmarks
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2021-03-22 14:42:42 -06:00 |
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tangxifan
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55d1004cf2
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[Benchmark] Add missing DPRAM module to LU32PEEng
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2021-03-22 14:41:38 -06:00 |
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tangxifan
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5fc83ebea3
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[Benchmark] Add missing DPRAM modules to LU8PEEng
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2021-03-22 14:38:00 -06:00 |
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tangxifan
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b828f91a78
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[Benchmark] Add missing DPRAM and SPRAM modules to mcml
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2021-03-22 14:13:05 -06:00 |
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tangxifan
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d050f1b746
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[Script] Enable fast bitstream generation for VTR benchmarks
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2021-03-22 12:54:36 -06:00 |
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tangxifan
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4bfd0c0a02
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[Test] Enable more VTR benchmark in testing
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2021-03-22 12:53:30 -06:00 |
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tangxifan
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b906ab814e
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[Benchmark] Add missing DPRAM module to mkPktMerge
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2021-03-22 12:51:23 -06:00 |
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tangxifan
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310c2a9495
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[Benchmark] Add missing DPRAM module to mkDelayWorker32B
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2021-03-22 12:51:02 -06:00 |
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tangxifan
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707247283c
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[Benchmark] Add missing DPRAM module to mkSMAdapter4B
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2021-03-22 12:50:39 -06:00 |
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tangxifan
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eb056e2afd
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[Benchmark] Add missing DPRAM module to or1200
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2021-03-22 12:50:17 -06:00 |
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tangxifan
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7fd345a616
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[Script] Solved the problem on BRAM mapping in the yosys script supporting both DSP and BRAMs
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2021-03-22 10:39:47 -06:00 |
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tangxifan
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cc10b10703
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[Test] Enable more benchmarks for testing; See problems when mapping BRAMs
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2021-03-20 22:53:37 -06:00 |
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tangxifan
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169ee53b79
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[Benchmark] Add missing modules to VTR benchmarks
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2021-03-20 22:53:17 -06:00 |
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tangxifan
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eca2a35612
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[Script] Add route chan width option to vtr openfpga script
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2021-03-20 22:00:09 -06:00 |
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tangxifan
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9a3aff274f
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[Test] Use fix routing channel width to save runtime for VTR benchmarks
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2021-03-20 21:59:44 -06:00 |
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tangxifan
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ca9a70fc88
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[Test] Comment out benchmarks have problems in synthesis
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2021-03-20 21:29:21 -06:00 |
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tangxifan
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125e94a6b3
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[Test] Add full VTR benchmark (with most commented); ready for massive testing
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2021-03-20 21:01:18 -06:00 |
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tangxifan
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2bd8ef2af9
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[Benchmark] Patch boundtop.v with missing SPRAM module
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2021-03-20 21:00:53 -06:00 |
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tangxifan
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cb07848475
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[Script] Remove verilog and SDC generation from vtr benchmark openfpga script; Focus on bitstream generation
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2021-03-20 18:11:54 -06:00 |
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tangxifan
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f3792bc6f6
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[Test] Update VTR benchmark test case to include DSP example benchmark
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2021-03-20 18:09:19 -06:00 |
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tangxifan
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477a522885
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[HDL] Rename tech lib to be consistent with arch name changes
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2021-03-20 18:08:03 -06:00 |
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tangxifan
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911979a731
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[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
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2021-03-20 18:04:59 -06:00 |
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tangxifan
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1185f7b8bf
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[Script] Add a template yosys script to enable DSP mapping
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2021-03-20 17:05:30 -06:00 |
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tangxifan
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6bf4880c50
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[benchmark] Add vtr benchmark
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2021-03-17 15:24:26 -06:00 |
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tangxifan
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f9dc7c1b54
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[HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells
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2021-03-17 15:15:22 -06:00 |
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tangxifan
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08a86e056a
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[Test] Add vtr benchmark regression test
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2021-03-17 15:13:58 -06:00 |
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tangxifan
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7eeb35d21f
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[Script] Bug fix in yosys script to synthesis BRAM
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2021-03-17 15:12:04 -06:00 |
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tangxifan
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1976a8068f
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[Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added)
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2021-03-17 15:11:17 -06:00 |
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tangxifan
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deee7ba366
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[Script] Add example script to run vtr benchmarks
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2021-03-17 15:10:56 -06:00 |
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tangxifan
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910f8471dd
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[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
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2021-03-17 15:10:05 -06:00 |
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tangxifan
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76113a80fa
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[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture
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2021-03-17 15:09:12 -06:00 |
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tangxifan
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e1f8b252b1
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Merge branch 'master' into yosys_heterogeneous_block_support
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2021-03-16 20:05:21 -06:00 |
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tangxifan
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d12a8a03fd
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[Test] Update test case using yosys bram parameters
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2021-03-16 19:52:17 -06:00 |
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tangxifan
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094b3e9b90
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[Script] Use parameters in template yosys script supporting BRAMs
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2021-03-16 19:51:48 -06:00 |