tangxifan
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aff73bdd74
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deployed edge sorting and make it as an option to link_arch command
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2020-03-08 15:59:53 -06:00 |
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tangxifan
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b80e26e711
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update bitstream generator to use sorted edges
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2020-03-08 15:36:47 -06:00 |
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tangxifan
|
5558932762
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use sorted edges in building routing modules
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2020-03-08 15:31:41 -06:00 |
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tangxifan
|
7a7f8374b3
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start deploying edge sorting in uniquifying SB modules
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2020-03-08 15:24:34 -06:00 |
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tangxifan
|
f9499afe04
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remove unused variable
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2020-03-08 15:00:01 -06:00 |
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tangxifan
|
0c7aa2581d
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update vpr8 version with hotfix on undriven pins in GSB
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2020-03-08 14:58:56 -06:00 |
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tangxifan
|
b219b096ee
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hotfix on removing dangling inputs from GSB, which are CLB direct output
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2020-03-08 13:54:49 -06:00 |
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tangxifan
|
b2534f1a09
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Merge branch 'refactoring' into dev
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2020-03-07 23:31:45 -07:00 |
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tangxifan
|
0fbf3fca41
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start developing edge sorting inside RRGSB
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2020-03-07 23:30:55 -07:00 |
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tangxifan
|
8b40ca2990
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Merge branch 'refactoring' into dev
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2020-03-07 17:54:13 -07:00 |
|
tangxifan
|
ca92c2717f
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bug fix for tile directs
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2020-03-07 16:00:32 -07:00 |
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tangxifan
|
e48c2b116d
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bug fixing for duplicated grid pin names
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2020-03-07 15:46:12 -07:00 |
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tangxifan
|
37423729ec
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bug fixing for naming the duplicated pins
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2020-03-07 15:44:57 -07:00 |
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tangxifan
|
3eeac94a6e
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Merge branch 'refactoring' into dev
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2020-03-06 20:58:07 -07:00 |
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tangxifan
|
c36c302052
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looks like tileable routing is working
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2020-03-06 17:16:53 -07:00 |
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tangxifan
|
f54f46483b
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start debugging tileable rr_graph generator
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2020-03-06 17:02:22 -07:00 |
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tangxifan
|
5be118d695
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tileable rr_graph builder ready to debug
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2020-03-06 16:18:45 -07:00 |
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tangxifan
|
245a379c4f
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start plug in tileable rr_graph builder
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2020-03-06 16:03:00 -07:00 |
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tangxifan
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3eb59d201f
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adapt top function of tileable rr_graph builder
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2020-03-06 15:24:26 -07:00 |
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tangxifan
|
441a307100
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add routing chan width corrector to rr_graph builder utils
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2020-03-06 14:54:40 -07:00 |
|
tangxifan
|
441de12936
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adapt Fc in gsb connection builder to use VPR8 Fc builder
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2020-03-06 14:43:12 -07:00 |
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tangxifan
|
ee4d5e46a0
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Merge branch 'refactoring' into dev
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2020-03-05 21:25:36 -07:00 |
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tangxifan
|
8d350ee22f
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adapt tileable rr_graph edge builder to rr_graph object
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2020-03-05 20:50:21 -07:00 |
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tangxifan
|
328488f357
|
adapt chan rr node builder to use rr_graph obj
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2020-03-05 20:15:16 -07:00 |
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tangxifan
|
3e3a523926
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Merge branch 'refactoring' into dev
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2020-03-05 17:48:43 -07:00 |
|
tangxifan
|
5067dd846e
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adapting channel rr_node builder for tileable rr_graph
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2020-03-05 17:47:48 -07:00 |
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tangxifan
|
850788eace
|
adapt tileable rr_graph node builder for rr_graph object
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2020-03-05 17:15:49 -07:00 |
|
tangxifan
|
5dcffb1a6e
|
Merge branch 'refactoring' into dev
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2020-03-05 15:36:16 -07:00 |
|
tangxifan
|
de62ce8872
|
add node builder for tileable rr_graph builder
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2020-03-05 15:34:04 -07:00 |
|
tangxifan
|
646ee90937
|
bring tileable gsb builder for rr_graph online
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2020-03-04 18:19:53 -07:00 |
|
tangxifan
|
4455615980
|
adapt tileable routing channel detail builder
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2020-03-04 14:21:35 -07:00 |
|
tangxifan
|
6e83154703
|
move rr_gsb and rr_chan to tileable rr_graph builder
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2020-03-04 14:14:28 -07:00 |
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tangxifan
|
4b7d2221d1
|
adapt rr_graph builder utilized functions and move rr_graph utils from openfpga to vpr
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2020-03-04 13:55:53 -07:00 |
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tangxifan
|
524798799c
|
start adapting tileable rr_graph builder. Bring channel node detail data structure online
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2020-03-04 11:21:34 -07:00 |
AurelienUoU
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aed3b01800
|
Directlist extension bug fix
|
2020-03-04 09:09:06 -07:00 |
|
tangxifan
|
9f13d3bc23
|
Merge branch 'refactoring' into dev
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2020-03-03 12:31:20 -07:00 |
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tangxifan
|
7fcd27e000
|
now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
|
2020-03-03 12:29:58 -07:00 |
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tangxifan
|
3241d8bd37
|
put analysis sdc writer online. Minor bug in redudant '/' to be fixed
|
2020-03-02 19:54:18 -07:00 |
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tangxifan
|
037c7e5c43
|
adapt top-level function for analysis SDC writer
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2020-03-02 17:58:44 -07:00 |
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tangxifan
|
24f7416c71
|
adapt analysis SDC writer for grids
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2020-03-02 17:15:01 -07:00 |
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tangxifan
|
6474183539
|
adapt analysis SDC writer for routing modules
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2020-03-02 14:29:58 -07:00 |
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tangxifan
|
543cff58b9
|
start porting analysis SDC writer
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2020-03-02 13:44:08 -07:00 |
|
tangxifan
|
7befcaba57
|
Merge branch 'refactoring' into dev
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2020-03-02 11:22:58 -07:00 |
|
tangxifan
|
a17c14c363
|
clean-up command addition and add fabric bitstream building to sample script
|
2020-03-02 10:39:19 -07:00 |
|
tangxifan
|
9fe8ff51f9
|
Merge branch 'refactoring' into dev
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2020-02-29 15:19:52 -07:00 |
|
tangxifan
|
aa66042dfb
|
move simulation setting annotation to a separated source file
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2020-02-29 15:19:02 -07:00 |
ganeshgore
|
ae4b0a6f9c
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2020-02-29 14:40:33 -07:00 |
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tangxifan
|
cf25f1f339
|
Merge branch 'refactoring' into dev
|
2020-02-29 13:30:00 -07:00 |
|
tangxifan
|
7b18f7cd09
|
now the auto select number of clocks in simulation is online
|
2020-02-29 13:29:16 -07:00 |
|
tangxifan
|
3807a940f4
|
fixed critical bugs in bitstream generation and now we pass microbenchmarks
|
2020-02-28 16:45:50 -07:00 |