adapt tileable rr_graph node builder for rr_graph object
This commit is contained in:
tangxifan
parent
de62ce8872
commit
850788eace
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@ -7,8 +7,14 @@
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#include "vtr_log.h"
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#include "vtr_geometry.h"
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/* Headers from openfpgautil library */
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#include "openfpga_side_manager.h"
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#include "vpr_types.h"
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#include "vpr_utils.h"
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#include "rr_node.h"
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#include "rr_graph_builder_utils.h"
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#include "tileable_chan_details_builder.h"
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#include "tileable_rr_graph_node_builder.h"
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@ -311,10 +317,11 @@ std::vector<size_t> estimate_num_rr_nodes(const DeviceGrid& grids,
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*
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* Note: ensure that there are NO nodes in the rr_graph
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***********************************************************************/
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void alloc_rr_graph_nodes(RRGraph& rr_graph,
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const DeviceGrid& grids,
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const vtr::Point<size_t>& chan_width,
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const std::vector<t_segment_inf>& segment_infs) {
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void alloc_tileable_rr_graph_nodes(RRGraph& rr_graph,
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vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
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const DeviceGrid& grids,
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const vtr::Point<size_t>& chan_width,
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const std::vector<t_segment_inf>& segment_infs) {
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VTR_ASSERT(0 == rr_graph.nodes().size());
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std::vector<size_t> num_rr_nodes_per_type = estimate_num_rr_nodes(grids, chan_width, segment_infs);
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@ -327,14 +334,319 @@ void alloc_rr_graph_nodes(RRGraph& rr_graph,
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rr_graph.reserve_nodes(num_nodes);
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/* Add nodes by types */
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for (const t_rr_type& node_type : {SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}) {
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for (size_t inode = 0; inode < num_rr_nodes_per_type[size_t(node_type)]; ++inode) {
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rr_graph.create_node(node_type);
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rr_node_driver_switches.reserve(num_nodes);
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}
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/************************************************************************
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* Configure OPIN rr_nodes for this grid
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* coordinates: xlow, ylow, xhigh, yhigh,
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* features: capacity, ptc_num (pin_num),
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*
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* Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!!
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***********************************************************************/
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static
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void load_one_grid_opin_nodes_basic_info(RRGraph& rr_graph,
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vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
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const vtr::Point<size_t>& grid_coordinate,
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const t_grid_tile& cur_grid,
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const e_side& io_side,
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const RRSwitchId& delayless_switch) {
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SideManager io_side_manager(io_side);
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/* Walk through the width height of each grid,
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* get pins and configure the rr_nodes
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*/
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for (int width = 0; width < cur_grid.type->width; ++width) {
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for (int height = 0; height < cur_grid.type->height; ++height) {
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/* Walk through sides */
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for (size_t side = 0; side < NUM_SIDES; ++side) {
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SideManager side_manager(side);
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/* skip unwanted sides */
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if ( (true == is_io_type(cur_grid.type))
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&& (side != io_side_manager.to_size_t()) ) {
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continue;
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}
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/* Find OPINs */
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/* Configure pins by pins */
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std::vector<int> opin_list = get_grid_side_pins(cur_grid, DRIVER, side_manager.get_side(),
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width, height);
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for (const int& pin_num : opin_list) {
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/* Create a new node and fill information */
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const RRNodeId& node = rr_graph.create_node(OPIN);
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/* node bounding box */
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rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x() + width,
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grid_coordinate.x() + width,
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grid_coordinate.y() + height,
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grid_coordinate.y() + height));
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rr_graph.set_node_side(node, side_manager.get_side());
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rr_graph.set_node_pin_num(node, pin_num);
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rr_graph.set_node_capacity(node, 1);
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/* cost index is a FIXED value for OPIN */
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rr_graph.set_node_cost_index(node, OPIN_COST_INDEX);
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/* Switch info */
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VTR_ASSERT(size_t(node) == rr_node_driver_switches.size());
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rr_node_driver_switches.push_back(delayless_switch);
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/* RC data */
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rr_graph.set_node_rc_data_index(node, find_create_rr_rc_data(0., 0.));
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} /* End of loading OPIN rr_nodes */
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} /* End of side enumeration */
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} /* End of height enumeration */
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} /* End of width enumeration */
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}
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/************************************************************************
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* Configure IPIN rr_nodes for this grid
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* coordinates: xlow, ylow, xhigh, yhigh,
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* features: capacity, ptc_num (pin_num),
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*
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* Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!!
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***********************************************************************/
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static
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void load_one_grid_ipin_nodes_basic_info(RRGraph& rr_graph,
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vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
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const vtr::Point<size_t>& grid_coordinate,
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const t_grid_tile& cur_grid,
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const e_side& io_side,
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const RRSwitchId& wire_to_ipin_switch) {
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SideManager io_side_manager(io_side);
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/* Walk through the width and height of each grid,
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* get pins and configure the rr_nodes
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*/
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for (int width = 0; width < cur_grid.type->width; ++width) {
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for (int height = 0; height < cur_grid.type->height; ++height) {
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/* Walk through sides */
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for (size_t side = 0; side < NUM_SIDES; ++side) {
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SideManager side_manager(side);
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/* skip unwanted sides */
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if ( (true == is_io_type(cur_grid.type))
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&& (side != io_side_manager.to_size_t()) ) {
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continue;
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}
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/* Find IPINs */
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/* Configure pins by pins */
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std::vector<int> ipin_list = get_grid_side_pins(cur_grid, RECEIVER, side_manager.get_side(), width, height);
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for (const int& pin_num : ipin_list) {
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/* Create a new node and fill information */
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const RRNodeId& node = rr_graph.create_node(IPIN);
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/* node bounding box */
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rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x() + width,
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grid_coordinate.x() + width,
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grid_coordinate.y() + height,
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grid_coordinate.y() + height));
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rr_graph.set_node_side(node, side_manager.get_side());
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rr_graph.set_node_pin_num(node, pin_num);
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rr_graph.set_node_capacity(node, 1);
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/* cost index is a FIXED value for OPIN */
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rr_graph.set_node_cost_index(node, IPIN_COST_INDEX);
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/* Switch info */
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VTR_ASSERT(size_t(node) == rr_node_driver_switches.size());
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rr_node_driver_switches.push_back(wire_to_ipin_switch);
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/* RC data */
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rr_graph.set_node_rc_data_index(node, find_create_rr_rc_data(0., 0.));
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} /* End of loading IPIN rr_nodes */
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} /* End of side enumeration */
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} /* End of height enumeration */
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} /* End of width enumeration */
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}
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/************************************************************************
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* Configure SOURCE rr_nodes for this grid
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* coordinates: xlow, ylow, xhigh, yhigh,
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* features: capacity, ptc_num (pin_num),
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*
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* Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!!
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***********************************************************************/
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static
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void load_one_grid_source_nodes_basic_info(RRGraph& rr_graph,
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vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
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const vtr::Point<size_t>& grid_coordinate,
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const t_grid_tile& cur_grid,
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const e_side& io_side,
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const RRSwitchId& delayless_switch) {
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SideManager io_side_manager(io_side);
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/* Set a SOURCE rr_node for each DRIVER class */
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for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) {
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/* Set a SINK rr_node for the OPIN */
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if (DRIVER != cur_grid.type->class_inf[iclass].type) {
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continue;
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}
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/* Create a new node and fill information */
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const RRNodeId& node = rr_graph.create_node(SOURCE);
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/* node bounding box */
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rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x(),
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grid_coordinate.x(),
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grid_coordinate.y(),
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grid_coordinate.y()));
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rr_graph.set_node_class_num(node, iclass);
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rr_graph.set_node_capacity(node, 1);
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/* The capacity should be the number of pins in this class*/
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rr_graph.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins);
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/* cost index is a FIXED value for SOURCE */
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rr_graph.set_node_cost_index(node, SOURCE_COST_INDEX);
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/* Switch info */
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VTR_ASSERT(size_t(node) == rr_node_driver_switches.size());
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rr_node_driver_switches.push_back(delayless_switch);
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/* RC data */
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rr_graph.set_node_rc_data_index(node, find_create_rr_rc_data(0., 0.));
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} /* End of class enumeration */
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}
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/************************************************************************
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* Configure SINK rr_nodes for this grid
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* coordinates: xlow, ylow, xhigh, yhigh,
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* features: capacity, ptc_num (pin_num),
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*
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* Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!!
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***********************************************************************/
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static
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void load_one_grid_sink_nodes_basic_info(RRGraph& rr_graph,
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vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
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const vtr::Point<size_t>& grid_coordinate,
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const t_grid_tile& cur_grid,
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const e_side& io_side,
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const RRSwitchId& delayless_switch) {
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SideManager io_side_manager(io_side);
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/* Set a SINK rr_node for each RECEIVER class */
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for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) {
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/* Set a SINK rr_node for the OPIN */
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if (RECEIVER != cur_grid.type->class_inf[iclass].type) {
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continue;
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}
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/* Create a new node and fill information */
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const RRNodeId& node = rr_graph.create_node(SINK);
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/* node bounding box */
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rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x(),
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grid_coordinate.x(),
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grid_coordinate.y(),
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grid_coordinate.y()));
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rr_graph.set_node_class_num(node, iclass);
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rr_graph.set_node_capacity(node, 1);
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/* The capacity should be the number of pins in this class*/
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rr_graph.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins);
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/* cost index is a FIXED value for SINK */
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rr_graph.set_node_cost_index(node, SINK_COST_INDEX);
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/* Switch info */
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VTR_ASSERT(size_t(node) == rr_node_driver_switches.size());
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rr_node_driver_switches.push_back(delayless_switch);
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/* RC data */
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rr_graph.set_node_rc_data_index(node, find_create_rr_rc_data(0., 0.));
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} /* End of class enumeration */
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}
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/************************************************************************
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* Create all the rr_nodes for grids
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***********************************************************************/
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static
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void load_grid_nodes_basic_info(RRGraph& rr_graph,
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vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
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const DeviceGrid& grids,
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const RRSwitchId& wire_to_ipin_switch,
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const RRSwitchId& delayless_switch) {
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for (size_t iy = 0; iy < grids.height(); ++iy) {
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for (size_t ix = 0; ix < grids.width(); ++ix) {
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/* Skip EMPTY tiles */
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if (true == is_empty_type(grids[ix][iy].type)) {
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continue;
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}
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/* We only build rr_nodes for grids with width_offset = 0 and height_offset = 0 */
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if ( (0 < grids[ix][iy].width_offset)
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|| (0 < grids[ix][iy].height_offset) ) {
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continue;
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}
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vtr::Point<size_t> grid_coordinate(ix, iy);
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enum e_side io_side = NUM_SIDES;
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/* If this is the block on borders, we consider IO side */
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if (true == is_io_type(grids[ix][iy].type)) {
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vtr::Point<size_t> io_device_size(grids.width() - 1, grids.height() - 1);
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io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate);
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}
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/* Configure source rr_nodes for this grid */
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load_one_grid_source_nodes_basic_info(rr_graph,
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rr_node_driver_switches,
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grid_coordinate,
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grids[ix][iy],
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io_side,
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delayless_switch);
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/* Configure sink rr_nodes for this grid */
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load_one_grid_sink_nodes_basic_info(rr_graph,
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rr_node_driver_switches,
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grid_coordinate,
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grids[ix][iy],
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io_side,
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delayless_switch);
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/* Configure opin rr_nodes for this grid */
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load_one_grid_opin_nodes_basic_info(rr_graph,
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rr_node_driver_switches,
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grid_coordinate,
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grids[ix][iy],
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io_side,
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delayless_switch);
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/* Configure ipin rr_nodes for this grid */
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load_one_grid_ipin_nodes_basic_info(rr_graph,
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rr_node_driver_switches,
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grid_coordinate,
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grids[ix][iy],
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io_side,
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wire_to_ipin_switch);
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}
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}
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}
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/************************************************************************
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* Create all the rr_nodes covering both grids and routing channels
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***********************************************************************/
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void create_tileable_rr_graph_nodes(RRGraph& rr_graph,
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vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
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const DeviceGrid& grids,
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const RRSwitchId& wire_to_ipin_switch,
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const RRSwitchId& delayless_switch) {
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load_grid_nodes_basic_info(rr_graph,
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rr_node_driver_switches,
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grids,
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wire_to_ipin_switch,
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delayless_switch);
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VTR_ASSERT(num_nodes == rr_graph.nodes().size());
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}
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} /* end namespace openfpga */
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@ -21,10 +21,17 @@
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/* begin namespace openfpga */
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namespace openfpga {
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void alloc_rr_graph_nodes(RRGraph& rr_graph,
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const DeviceGrid& grids,
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const vtr::Point<size_t>& chan_width,
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const std::vector<t_segment_inf>& segment_infs);
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void alloc_tileable_rr_graph_nodes(RRGraph& rr_graph,
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vtr::vector<RRNodeId, RRSwitchId>& driver_switches,
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const DeviceGrid& grids,
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const vtr::Point<size_t>& chan_width,
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const std::vector<t_segment_inf>& segment_infs);
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void create_tileable_rr_graph_nodes(RRGraph& rr_graph,
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vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
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const DeviceGrid& grids,
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const RRSwitchId& wire_to_ipin_switch,
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const RRSwitchId& delayless_switch);
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} /* end namespace openfpga */
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