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OpenFPGA
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looks like tileable routing is working

This commit is contained in:
tangxifan 2020-03-06 17:16:53 -07:00
parent f54f46483b
commit c36c302052
1 changed files with 4 additions and 4 deletions
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8
vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
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@ -376,8 +376,8 @@ void load_one_grid_opin_nodes_basic_info(RRGraph& rr_graph,
/* node bounding box */
rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x() + width,
grid_coordinate.x() + width,
grid_coordinate.y() + height,
grid_coordinate.x() + width,
grid_coordinate.y() + height));
rr_graph.set_node_side(node, side_manager.get_side());
rr_graph.set_node_pin_num(node, pin_num);
@ -439,8 +439,8 @@ void load_one_grid_ipin_nodes_basic_info(RRGraph& rr_graph,
/* node bounding box */
rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x() + width,
grid_coordinate.x() + width,
grid_coordinate.y() + height,
grid_coordinate.x() + width,
grid_coordinate.y() + height));
rr_graph.set_node_side(node, side_manager.get_side());
rr_graph.set_node_pin_num(node, pin_num);
@ -491,8 +491,8 @@ void load_one_grid_source_nodes_basic_info(RRGraph& rr_graph,
/* node bounding box */
rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x(),
grid_coordinate.x(),
grid_coordinate.y(),
grid_coordinate.x(),
grid_coordinate.y()));
rr_graph.set_node_class_num(node, iclass);
@ -542,8 +542,8 @@ void load_one_grid_sink_nodes_basic_info(RRGraph& rr_graph,
/* node bounding box */
rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x(),
grid_coordinate.x(),
grid_coordinate.y(),
grid_coordinate.x(),
grid_coordinate.y()));
rr_graph.set_node_class_num(node, iclass);