adapt chan rr node builder to use rr_graph obj
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tangxifan
parent
5067dd846e
commit
328488f357
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@ -738,12 +738,222 @@ void load_one_chan_rr_nodes_basic_info(RRGraph& rr_graph,
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}
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}
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/************************************************************************
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* Initialize the basic information of X-channel rr_nodes:
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* coordinates: xlow, ylow, xhigh, yhigh,
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* features: capacity, track_ids, ptc_num, direction
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* grid_info : pb_graph_pin
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***********************************************************************/
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static
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void load_chanx_rr_nodes_basic_info(RRGraph& rr_graph,
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vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
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std::map<RRNodeId, std::vector<size_t>>& rr_node_track_ids,
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const DeviceGrid& grids,
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const size_t& chan_width,
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const std::vector<t_segment_inf>& segment_infs) {
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/* For X-direction Channel: CHANX */
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for (size_t iy = 0; iy < grids.height() - 1; ++iy) {
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/* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */
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std::vector<size_t> track_node_ids;
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for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
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vtr::Point<size_t> chanx_coord(ix, iy);
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/* Bypass if the routing channel does not exist */
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if (false == is_chanx_exist(grids, chanx_coord)) {
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continue;
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}
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bool force_start = false;
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bool force_end = false;
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/* All the tracks have to start when
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* - the routing channel touch the RIGHT side a heterogeneous block
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* - the routing channel touch the LEFT side of FPGA
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*/
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if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord)) {
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force_start = true;
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}
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/* All the tracks have to end when
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* - the routing channel touch the LEFT side a heterogeneous block
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* - the routing channel touch the RIGHT side of FPGA
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*/
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if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord)) {
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force_end = true;
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}
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ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2,
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force_start, force_end, segment_infs);
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/* Force node_ids from the previous chanx */
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if (0 < track_node_ids.size()) {
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/* Rotate should be done based on a typical case of routing tracks.
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* Tracks on the borders are not regularly started and ended,
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* which causes the node_rotation malfunction
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*/
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ChanNodeDetails chanx_details_tt = build_unidir_chan_node_details(chan_width, grids.width() - 2,
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false, false, segment_infs);
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chanx_details_tt.set_track_node_ids(track_node_ids);
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/* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */
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/* For INC_DIRECTION, we use clockwise rotation
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* node_id A ----> -----> node_id D
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* node_id B ----> / ----> node_id A
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* node_id C ----> / ----> node_id B
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* node_id D ----> ----> node_id C
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*/
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chanx_details_tt.rotate_track_node_id(1, INC_DIRECTION, true);
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/* For DEC_DIRECTION, we use clockwise rotation
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* node_id A <----- <----- node_id B
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* node_id B <----- \ <----- node_id C
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* node_id C <----- \ <----- node_id D
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* node_id D <----- <----- node_id A
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*/
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chanx_details_tt.rotate_track_node_id(1, DEC_DIRECTION, false);
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track_node_ids = chanx_details_tt.get_track_node_ids();
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chanx_details.set_track_node_ids(track_node_ids);
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}
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/* Configure CHANX in this channel */
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load_one_chan_rr_nodes_basic_info(rr_graph,
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rr_node_driver_switches,
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rr_node_track_ids,
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chanx_coord, CHANX,
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chanx_details,
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segment_infs,
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CHANX_COST_INDEX_START);
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/* Get a copy of node_ids */
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track_node_ids = chanx_details.get_track_node_ids();
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}
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}
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}
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/************************************************************************
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* Initialize the basic information of Y-channel rr_nodes:
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* coordinates: xlow, ylow, xhigh, yhigh,
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* features: capacity, track_ids, ptc_num, direction
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***********************************************************************/
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static
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void load_chany_rr_nodes_basic_info(RRGraph& rr_graph,
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vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
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std::map<RRNodeId, std::vector<size_t>>& rr_node_track_ids,
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const DeviceGrid& grids,
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const size_t& chan_width,
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const std::vector<t_segment_inf>& segment_infs) {
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/* For Y-direction Channel: CHANY */
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for (size_t ix = 0; ix < grids.width() - 1; ++ix) {
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/* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */
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std::vector<size_t> track_node_ids;
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for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
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vtr::Point<size_t> chany_coord(ix, iy);
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/* Bypass if the routing channel does not exist */
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if (false == is_chany_exist(grids, chany_coord)) {
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continue;
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}
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bool force_start = false;
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bool force_end = false;
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/* All the tracks have to start when
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* - the routing channel touch the TOP side a heterogeneous block
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* - the routing channel touch the BOTTOM side of FPGA
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*/
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if (true == is_chany_top_to_multi_width_grid(grids, chany_coord)) {
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force_start = true;
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}
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/* All the tracks have to end when
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* - the routing channel touch the BOTTOM side a heterogeneous block
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* - the routing channel touch the TOP side of FPGA
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*/
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if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord)) {
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force_end = true;
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}
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ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2,
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force_start, force_end, segment_infs);
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/* Force node_ids from the previous chanx */
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if (0 < track_node_ids.size()) {
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/* Rotate should be done based on a typical case of routing tracks.
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* Tracks on the borders are not regularly started and ended,
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* which causes the node_rotation malfunction
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*/
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ChanNodeDetails chany_details_tt = build_unidir_chan_node_details(chan_width, grids.height() - 2,
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false, false, segment_infs);
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chany_details_tt.set_track_node_ids(track_node_ids);
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/* Rotate the chany_details by an offset of 1*/
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/* For INC_DIRECTION, we use clockwise rotation
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* node_id A ----> -----> node_id D
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* node_id B ----> / ----> node_id A
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* node_id C ----> / ----> node_id B
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* node_id D ----> ----> node_id C
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*/
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chany_details_tt.rotate_track_node_id(1, INC_DIRECTION, true);
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/* For DEC_DIRECTION, we use clockwise rotation
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* node_id A <----- <----- node_id B
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* node_id B <----- \ <----- node_id C
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* node_id C <----- \ <----- node_id D
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* node_id D <----- <----- node_id A
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*/
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chany_details_tt.rotate_track_node_id(1, DEC_DIRECTION, false);
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track_node_ids = chany_details_tt.get_track_node_ids();
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chany_details.set_track_node_ids(track_node_ids);
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}
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/* Configure CHANX in this channel */
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load_one_chan_rr_nodes_basic_info(rr_graph,
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rr_node_driver_switches,
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rr_node_track_ids,
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chany_coord, CHANY,
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chany_details,
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segment_infs,
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CHANX_COST_INDEX_START + segment_infs.size());
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/* Get a copy of node_ids */
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track_node_ids = chany_details.get_track_node_ids();
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}
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}
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}
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/************************************************************************
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* Reverse the track_ids of CHANX and CHANY nodes in DEC_DIRECTION
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* This is required as the track ids are allocated in the sequence
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* of incrementing x and y
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* However, DEC direction routing tracks should have a reversed sequence in
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* track ids
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***********************************************************************/
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static
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void reverse_dec_chan_rr_node_track_ids(const RRGraph& rr_graph,
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std::map<RRNodeId, std::vector<size_t>>& rr_node_track_ids) {
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for (const RRNodeId& node : rr_graph.nodes()) {
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/* Bypass condition: only focus on CHANX and CHANY in DEC_DIRECTION */
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if ( (CHANX != rr_graph.node_type(node))
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&& (CHANY != rr_graph.node_type(node)) ) {
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continue;
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}
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/* Reach here, we must have a node of CHANX or CHANY */
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if (DEC_DIRECTION != rr_graph.node_direction(node)) {
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continue;
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}
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std::reverse(rr_node_track_ids[node].begin(),
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rr_node_track_ids[node].end() );
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}
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}
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/************************************************************************
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* Create all the rr_nodes covering both grids and routing channels
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***********************************************************************/
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void create_tileable_rr_graph_nodes(RRGraph& rr_graph,
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vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
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std::map<RRNodeId, std::vector<size_t>>& rr_node_track_ids,
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const DeviceGrid& grids,
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const vtr::Point<size_t>& chan_width,
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const std::vector<t_segment_inf>& segment_infs,
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const RRSwitchId& wire_to_ipin_switch,
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const RRSwitchId& delayless_switch) {
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load_grid_nodes_basic_info(rr_graph,
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@ -752,6 +962,23 @@ void create_tileable_rr_graph_nodes(RRGraph& rr_graph,
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wire_to_ipin_switch,
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delayless_switch);
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load_chanx_rr_nodes_basic_info(rr_graph,
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rr_node_driver_switches,
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rr_node_track_ids,
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grids,
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chan_width.x(),
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segment_infs);
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load_chany_rr_nodes_basic_info(rr_graph,
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rr_node_driver_switches,
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rr_node_track_ids,
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grids,
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chan_width.y(),
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segment_infs);
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reverse_dec_chan_rr_node_track_ids(rr_graph,
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rr_node_track_ids);
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}
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} /* end namespace openfpga */
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@ -29,10 +29,14 @@ void alloc_tileable_rr_graph_nodes(RRGraph& rr_graph,
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void create_tileable_rr_graph_nodes(RRGraph& rr_graph,
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vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
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std::map<RRNodeId, std::vector<size_t>>& rr_node_track_ids,
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const DeviceGrid& grids,
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const vtr::Point<size_t>& chan_width,
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const std::vector<t_segment_inf>& segment_infs,
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const RRSwitchId& wire_to_ipin_switch,
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const RRSwitchId& delayless_switch);
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} /* end namespace openfpga */
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#endif
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