3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
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* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
9a906e787b
[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock
2021-01-13 15:43:31 -07:00
7af6d7f07d
[Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation
2021-01-13 15:38:44 -07:00
91f12071d5
[Test] Use counter4bit in the multi-clock test
2021-01-13 13:34:59 -07:00
ccf3e037ff
[Benchmark] Change multi-clock counter from 8-bit to 4-bit
2021-01-13 13:31:06 -07:00
3790f2c26a
[Benchmark] Add 2-clock micro benchmark
2021-01-12 17:48:52 -07:00
6521aa2e7a
[Benchmark] Bug fix in pipelined and2 benchmark
2021-01-10 10:27:59 -07:00
4412bbd084
[Benchmark] Add a micro benchmark to test pipelined architecture
2021-01-10 10:21:30 -07:00
367cf59efd
[Benchmark] Bug fix in the and2_or2 benchmark
2020-09-17 10:35:13 -06:00
de48b8c7b2
[Benchmark] Add a new micro benchmark to test fracturable LUTs
2020-09-17 10:21:25 -06:00
f33422d4d7
add regression test to track runtime on big fpga devices using practical benchmarks
2020-07-28 12:38:42 -06:00
5d83abb2cf
bug fix in read architecture bitstream and regression tests
2020-07-27 19:37:05 -06:00
cec6bf0b6f
add or2 microbenchmark for testing external arch bitstream
2020-07-27 15:59:03 -06:00
92c3449999
bug fix in the regression test due to benchmark changes
2020-07-22 13:17:05 -06:00
7d39e136a4
enrich micro benchmarks
2020-07-22 12:33:52 -06:00
c87dbc4880
start using counter benchmark in regression tests
2020-06-11 19:31:15 -06:00
98a658a013
bug fixed in routing_test.v. Deployed to regression tests
2020-06-11 19:31:01 -06:00
f6cea1e17c
Added test_mode_low benchmark
2020-06-11 19:31:01 -06:00
3c781b18d3
Added routing benchmark
2020-06-11 19:31:01 -06:00
9761d13eef
update microbenchmark and2 module name
2020-04-20 13:37:39 -06:00
489ca75230
adapt benchmark and_latch module name to be different than benchmark and
2020-04-20 13:15:05 -06:00
8b03ec900f
fine-tune micro benchmark to fit port mapping in testbenches
2020-04-19 17:05:12 -06:00
32ed609238
update micro benchmark set and regression tests using them
2020-04-19 12:49:07 -06:00
eb3b02277a
Added XML and benchmarks for testing
2020-04-06 00:32:06 -06:00
d391983e8c
passing regression test on dpram benchmarks
2019-11-07 14:57:46 -07:00
56b4ee008e
add test for heterogeneous FPGA and fix bugs
2019-11-06 17:45:11 -07:00
dc241e6c03
add explicit port mapping support in testbenches; remove dangling ports in benchmarks
2019-11-02 23:03:47 -06:00
a6a3e7c36b
adding mcnc_big20 to regression test
2019-10-31 19:31:27 -06:00
5cb3717433
add single mode test case to regression test. debugging now
2019-10-28 15:57:17 -06:00
30cbe38d3d
Added Test Modes - Added blif VPR Option
2019-08-22 17:00:59 -06:00
b82369dd96
Added first draft of fpga_task script
2019-08-09 00:17:06 -06:00
AurelienAlacchi
tangxifan
CHARAS SAMY
ganeshgore