Ashton Snelgrove
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bd57662a9e
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Copy openfpga_flow into master image.
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2021-01-22 15:37:45 -07:00 |
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Ashton Snelgrove
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a45b9cb801
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Add OPENFPGA_PATH env variable to master dockerfile.
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2021-01-22 15:30:01 -07:00 |
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Ashton Snelgrove
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22144924fc
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Restore conditionals.
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2021-01-22 10:52:21 -07:00 |
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Ashton Snelgrove
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a6b97db314
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Trigger master image build.
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2021-01-22 10:16:44 -07:00 |
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Ashton Snelgrove
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cb80a9bbd4
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Merge remote-tracking branch 'origin/master' into github-action-optimizations
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2021-01-22 10:12:12 -07:00 |
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Ashton Snelgrove
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8cca1c63c3
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Fix dockerfile for master build to include yosys/share, and fix conditionals.
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2021-01-21 16:40:09 -07:00 |
Lalit Narain Sharma
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1823eb857d
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Merge pull request #177 from lnis-uofu/bump_yosys_submodule
Bumping the latest changes in yosys sub-module related to yosys synth…
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2021-01-21 09:40:29 +05:30 |
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Ashton Snelgrove
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f956f28792
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Update docker images, remove runtime/test split
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2021-01-20 14:20:12 -07:00 |
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Ashton Snelgrove
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5f613c46f7
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Switch code change check to a script
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2021-01-20 12:40:18 -07:00 |
tangxifan
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815468ac65
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[Doc] Add shortcut to call pin constraint option to documentation
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2021-01-20 09:20:51 -07:00 |
Lalit Sharma
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df073c327e
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Bumping the latest changes in yosys sub-module related to yosys synthesis for openfpga quicklogic device
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2021-01-20 07:23:51 -08:00 |
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tangxifan
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977ff52cb1
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[Doc] Format openfpga command documentation by using option views
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2021-01-19 20:26:38 -07:00 |
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tangxifan
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e9dc708d66
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[Doc] Group file format documentation into a unified section
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2021-01-19 19:44:44 -07:00 |
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tangxifan
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3a69ece199
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Merge pull request #175 from lnis-uofu/dev
Pin Constraint Support in Testbench Generation
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2021-01-19 19:24:10 -07:00 |
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tangxifan
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3f80a26172
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[Tool] Bug fix for combinational benchmarks in pre-config testbench generation
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2021-01-19 18:22:50 -07:00 |
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tangxifan
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ac8c63553a
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[Doc] Add file format index file
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2021-01-19 18:07:53 -07:00 |
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tangxifan
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fbb5c0cf8f
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[Doc] Add pin constraints to documentation
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2021-01-19 18:04:45 -07:00 |
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tangxifan
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af0646260c
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[Test] Bug fix in pin constraints
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2021-01-19 17:44:05 -07:00 |
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tangxifan
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186f2f1968
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[Test] Use pin constraint in multi-clock test case
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2021-01-19 17:42:40 -07:00 |
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tangxifan
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3fdd5ae8b3
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[Script] Use pin constraints in template script
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2021-01-19 17:42:25 -07:00 |
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tangxifan
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75b99b78e9
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[Tool] Now testbench generator consider pin constraints in generating clock sources for benchmarks
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2021-01-19 17:38:51 -07:00 |
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tangxifan
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da200658c1
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[Tool] Now autocheck top testbench consider pin constraints to generate operating clock sources for benchmarks
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2021-01-19 17:29:59 -07:00 |
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tangxifan
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0670c2de59
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[Tool] Deploy pin constraints to preconfig Verilog module generation
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2021-01-19 16:56:30 -07:00 |
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tangxifan
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e17a5cbbf2
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[Test] Rename to pin constraint to comply with libpcf requirement
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2021-01-19 15:52:51 -07:00 |
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tangxifan
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ecd955124b
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[Lib] Add libpcf to CMakelist and bug fix
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2021-01-19 15:51:14 -07:00 |
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tangxifan
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52ac7826eb
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[Lib] Add a library of parser/writer for pin constraint file (PCF)
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2021-01-19 15:45:45 -07:00 |
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tangxifan
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ab25e1af5f
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[Test] Add example XML for net mapping between benchmark to FPGA
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2021-01-19 09:29:21 -07:00 |
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tangxifan
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17c49711d3
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Merge pull request #174 from lnis-uofu/dev
Support Design Constraints for Repack
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2021-01-17 17:41:53 -07:00 |
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tangxifan
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c7f02601ab
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[Doc] Add repack design constraints to documentation
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2021-01-17 12:59:46 -07:00 |
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tangxifan
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8c311b8282
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[Tool] Bug fix in repacker for considering design constraints
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2021-01-17 12:26:14 -07:00 |
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tangxifan
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ea9d6bfe91
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[Flow] Update the design constraint file to follow bug fix in parser
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2021-01-17 10:41:01 -07:00 |
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tangxifan
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113119bd8e
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[Lib] Fix the bug in repack design constraint parser
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2021-01-17 10:39:55 -07:00 |
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tangxifan
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dd74f05a31
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[Test] Add repack constraints to tests
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2021-01-17 10:35:36 -07:00 |
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tangxifan
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12e0efd03e
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[Script] Add an example openfpga script to use repack design constraints
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2021-01-17 10:33:56 -07:00 |
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tangxifan
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2efe513122
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[Tool] Now repack consider design constraints; test pending
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2021-01-16 21:57:17 -07:00 |
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tangxifan
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d0e05b3575
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[Lib] Now use pb_type in design constraints instead of physical tiles
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2021-01-16 21:35:43 -07:00 |
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tangxifan
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bb8e7e25c2
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[Tool] Start deploying design constraints in repack engine
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2021-01-16 21:27:12 -07:00 |
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tangxifan
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b86adabe69
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[Lib] Remove unused data storage from repack design constraints
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2021-01-16 21:14:52 -07:00 |
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tangxifan
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fa67517349
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[Tool] Add repack design constraints to openfpga command 'repack'
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2021-01-16 18:49:34 -07:00 |
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tangxifan
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706e84bb62
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[Lib] Bug fix in testing program
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2021-01-16 18:15:56 -07:00 |
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tangxifan
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67c54c4d3b
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[Lib] Bug fix in the repack design constraint lib
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2021-01-16 17:34:22 -07:00 |
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tangxifan
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ad7a54db1b
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[Tool] Add repack dc library to compilation
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2021-01-16 17:20:59 -07:00 |
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tangxifan
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9d80f1ab39
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[Lib] Add test program to the library of repack design constraints
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2021-01-16 17:18:42 -07:00 |
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tangxifan
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03b5bcc244
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[Lib] Add XML writer for repack design constraints
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2021-01-16 17:15:31 -07:00 |
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tangxifan
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2a7601fb7e
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[Lib] Add libarchopenfpga to the dependency of librepackdesignconstraints
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2021-01-16 17:14:51 -07:00 |
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tangxifan
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f1bfa2ef8c
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[Lib] Add XML parser for repack design constraints
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2021-01-16 17:03:01 -07:00 |
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tangxifan
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8be12b6e82
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[Lib] Add example design constraint file
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2021-01-16 16:36:10 -07:00 |
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tangxifan
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a926c74ae5
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[Lib] Add CMake script to compile the repack design constraint library
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2021-01-16 16:35:46 -07:00 |
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tangxifan
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b57dc7b898
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[Lib] Add repack design constraint library
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2021-01-16 16:35:13 -07:00 |
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tangxifan
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8578c1ecac
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[Flow] Rename the design contraint file syntax
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2021-01-16 15:35:13 -07:00 |