ganeshgore
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a42342fa9e
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Merge pull request #402 from lnis-uofu/yosys+verific_support
Adding Yosys+Verific support.
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2021-11-02 15:22:48 -06:00 |
Aram Kostanyan
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a707226ba6
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Added 'basic_tests/verific_test' test case into regression tests suite.
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2021-11-01 18:33:33 +05:00 |
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Aram Kostanyan
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b332a5a1b4
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Added 'basic_tests/verific_test' test-case.
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2021-11-01 18:20:57 +05:00 |
tangxifan
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0d882f57b1
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Merge branch 'master' into yosys+verific_support
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2021-10-30 22:49:21 -07:00 |
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tangxifan
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4e50644ea8
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Merge pull request #403 from lnis-uofu/yosyshq
Use Yosys HQ v0.10 as a submodule
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2021-10-30 20:57:49 -07:00 |
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tangxifan
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0d14aa4cb8
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[Flow] Add comments to clarify the limitations
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2021-10-30 19:17:11 -07:00 |
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tangxifan
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7f999d03c6
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[Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade
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2021-10-30 18:05:39 -07:00 |
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tangxifan
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370e3fef83
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[Test] Now use pre-configured testbench when verifying signal gen microbenchmarks
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2021-10-30 18:03:59 -07:00 |
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tangxifan
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7455990ead
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[Flow] bug fix
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2021-10-30 16:52:32 -07:00 |
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tangxifan
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c8e9dfbeda
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[Test] bug fix
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2021-10-30 16:50:57 -07:00 |
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tangxifan
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27b82d1473
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[Flow] bug fix
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2021-10-30 16:09:31 -07:00 |
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tangxifan
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a4cfc84930
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[Test] Bug fix
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2021-10-30 16:00:47 -07:00 |
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tangxifan
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335347a74f
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[Test] Bug fix
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2021-10-30 15:48:25 -07:00 |
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tangxifan
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6277234125
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[Flow] bug fix in BRAM-oriented yosys scripts
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2021-10-30 15:34:30 -07:00 |
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tangxifan
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be47e78289
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[Arch] Change arch for Sapone test
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2021-10-30 15:23:19 -07:00 |
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tangxifan
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e6cc3c4942
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[Flow] Enable flatten for dff-related yosys scripts
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2021-10-30 15:12:34 -07:00 |
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tangxifan
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ad5cce0ae8
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[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
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2021-10-30 15:11:07 -07:00 |
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tangxifan
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8dea7e80e6
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[Flow] Update yosys script to not use sdff and dffe
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2021-10-30 14:56:54 -07:00 |
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tangxifan
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40d11a45d9
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[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
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2021-10-30 14:49:56 -07:00 |
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tangxifan
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b7ad61227d
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[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF
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2021-10-30 14:47:37 -07:00 |
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tangxifan
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ec184ef532
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[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF
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2021-10-30 14:46:12 -07:00 |
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tangxifan
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0b770f3330
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[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
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2021-10-30 14:36:43 -07:00 |
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tangxifan
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59a622a910
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[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
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2021-10-30 14:34:37 -07:00 |
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tangxifan
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978c60e75b
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[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
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2021-10-30 13:29:38 -07:00 |
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tangxifan
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18bab18032
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[Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release
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2021-10-30 13:20:58 -07:00 |
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tangxifan
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16de60e943
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[Test] Turn off ACE2 run in bitstream generation only flows
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2021-10-30 12:31:14 -07:00 |
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tangxifan
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94328351be
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[Script] Replace deprecated ``rmdff`` in out-of-date yosys scripts
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2021-10-30 12:00:06 -07:00 |
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tangxifan
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91627abe12
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[FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided
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2021-10-30 11:53:46 -07:00 |
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tangxifan
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0a449cc24c
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[HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected
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2021-10-30 11:45:01 -07:00 |
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tangxifan
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9c06041ce4
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[Flow] Update yosys script by replacing the deprecated command 'opt_rmdff` with `opt_dff`
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2021-10-30 11:27:40 -07:00 |
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tangxifan
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e8b3c68565
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[Github] Now use YosysHQ v0.10 release as a submodule
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2021-10-29 14:19:26 -07:00 |
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tangxifan
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104e177e37
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[Git] Update yosys submodule:
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2021-10-29 14:17:42 -07:00 |
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tangxifan
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aece87b0c8
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[Github] debugging
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2021-10-29 14:15:16 -07:00 |
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tangxifan
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39fa050b3b
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[Github] debugging
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2021-10-29 14:13:02 -07:00 |
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tangxifan
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f2ce2e6126
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[Github] debugging
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2021-10-29 14:11:45 -07:00 |
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tangxifan
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b213faaf81
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[Git] Add YosysHQ as a submodule in the place of QuickLogic Yosys
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2021-10-29 13:54:15 -07:00 |
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Aram Kostanyan
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a355977420
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Adding Yosys+Verific support.
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2021-10-29 18:34:27 +05:00 |
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tangxifan
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ddf96fc23a
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Merge pull request #397 from lnis-uofu/gg_ci_cd_dev
Updated CI documentation
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2021-10-28 15:27:37 -07:00 |
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tangxifan
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2d9ecb5678
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Merge pull request #400 from lnis-uofu/mult_36
Fixed port names for mult_36x36
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2021-10-27 09:35:42 -07:00 |
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Aram Kostanyan
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2eef21a1af
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Fixed port names for mult_36x36
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2021-10-26 19:14:43 +05:00 |
Ganesh Gore
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130805d50c
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Updated CI documentation
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2021-10-21 15:17:30 -06:00 |
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tangxifan
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c35c9bad55
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Merge pull request #396 from lnis-uofu/gg_ci_cd_dev
[Bugfix] CI docker image build
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2021-10-20 15:02:43 -07:00 |
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ganeshgore
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c5f00900a9
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Merge branch 'master' into gg_ci_cd_dev
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2021-10-20 15:00:13 -06:00 |
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Ganesh Gore
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f0d81f7ffc
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[Bugfix] docker CI build
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2021-10-20 14:50:17 -06:00 |
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tangxifan
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5e912b3c51
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Merge pull request #392 from lnis-uofu/gg_ci_cd_dev
Make CI Portable
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2021-10-19 08:33:38 -07:00 |
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Ganesh Gore
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de53943208
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Removed dummy changes
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2021-10-18 21:43:05 -06:00 |
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Ganesh Gore
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ba7a676429
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Updated docker yml
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2021-10-18 21:42:39 -06:00 |
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Ganesh Gore
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ed5942ce56
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Added DOCKER_REPO variable
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2021-10-18 20:00:21 -06:00 |
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Ganesh Gore
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32f234f4fc
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Made LNIS Repo as default
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2021-10-18 12:54:31 -06:00 |
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Ganesh Gore
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fdc9e318fd
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[CI] Addding conditional docker push
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2021-10-18 12:18:35 -06:00 |