tangxifan
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a0b150f12e
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adding micro architecture using adder chain
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2020-03-20 14:18:59 -06:00 |
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tangxifan
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29450f3472
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debugging multi-source lb router
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2020-03-12 20:42:41 -06:00 |
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tangxifan
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2a260a05aa
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add a microbenchmark `and_latch` to test LUTs in wired mode
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2020-03-11 10:40:59 -06:00 |
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tangxifan
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aff73bdd74
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deployed edge sorting and make it as an option to link_arch command
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2020-03-08 15:59:53 -06:00 |
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tangxifan
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3241d8bd37
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put analysis sdc writer online. Minor bug in redudant '/' to be fixed
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2020-03-02 19:54:18 -07:00 |
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tangxifan
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a17c14c363
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clean-up command addition and add fabric bitstream building to sample script
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2020-03-02 10:39:19 -07:00 |
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tangxifan
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7b18f7cd09
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now the auto select number of clocks in simulation is online
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2020-02-29 13:29:16 -07:00 |
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tangxifan
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9fd184e3ab
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rm out-of-date script
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2020-02-28 15:42:18 -07:00 |
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tangxifan
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05ebd77d7d
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start debugging with micro benchmarks. Spot problem in local routing
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2020-02-28 15:41:32 -07:00 |
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tangxifan
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80bb2baae5
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start verification and bug fixing
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2020-02-28 14:29:01 -07:00 |
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tangxifan
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092e10afda
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bring pnr sdc generator online and fixed minor bugs in bitstream writing
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2020-02-28 11:14:50 -07:00 |
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tangxifan
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65c81e14b2
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add simulation ini file writer
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2020-02-27 18:01:47 -07:00 |
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tangxifan
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078f72320f
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debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
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2020-02-27 13:24:26 -07:00 |
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tangxifan
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25e0583636
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add io location map data structure and start porting verilog testbench generator
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2020-02-26 17:10:57 -07:00 |
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tangxifan
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a26d31b87f
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make write bitstream online
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2020-02-26 11:09:23 -07:00 |
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tangxifan
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51439ba3b4
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add bitstream writer to be integrated
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2020-02-23 20:40:18 -07:00 |
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tangxifan
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b035b4c87f
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debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
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2020-02-21 12:16:50 -07:00 |
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tangxifan
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3e07d7d5e0
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finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
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2020-02-20 20:26:20 -07:00 |
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tangxifan
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fdb27c5a6b
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move lb_rr_graph construction to repack command
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2020-02-20 13:24:34 -07:00 |
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tangxifan
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409b3f6896
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add lb_rr_graph builder for the refactored version
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2020-02-17 21:11:56 -07:00 |
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tangxifan
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c6c3ef71f3
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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tangxifan
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8b0df8632c
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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tangxifan
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13fadd0f91
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move compact routing hierarchy to build_fabric command
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2020-02-12 15:49:47 -07:00 |
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tangxifan
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175bef014a
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add compact_routing hierarchy command
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2020-02-11 17:40:37 -07:00 |
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tangxifan
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ed9e038845
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add functionality of LUT truth table fix-up
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2020-02-06 17:14:29 -07:00 |
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tangxifan
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dad204674b
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done an initial version of clustering net fix-up based on routing results. Debugging on the way
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2020-02-05 21:50:52 -07:00 |
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tangxifan
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5006a4395d
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bring RRGraph object and writer online
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2020-01-31 16:39:40 -07:00 |
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tangxifan
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02d6256e95
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pass simple test on pb_type annotation for frac_lut5 architecture
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2020-01-30 21:39:44 -07:00 |
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tangxifan
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568ed120c2
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change report naming fix-up to be XML format
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2020-01-29 21:53:56 -07:00 |
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tangxifan
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2dc4c26257
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add naming fix-up
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2020-01-29 17:49:33 -07:00 |
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tangxifan
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8c86c0af04
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add check netlist naming conflict command and functions
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2020-01-29 16:23:41 -07:00 |
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tangxifan
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bb7fa2af77
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add pb interconnect binding to circuit model
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2020-01-28 17:04:10 -07:00 |
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tangxifan
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5ecb771673
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debugging the annotation to physical mode of pb_types
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2020-01-27 17:43:22 -07:00 |
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tangxifan
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2e41138633
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use a micro benchmark for vpr quick-run
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2020-01-26 17:56:22 -07:00 |
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tangxifan
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93ab4b8dd2
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add test case for openfpga shell
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2020-01-26 17:30:46 -07:00 |