tangxifan
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4b9431b132
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[test] avoid XML bitstream output when can go beyond github runners' disk space
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2022-05-25 18:45:26 +08:00 |
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tangxifan
|
9832722056
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[test] now add QuickLogic memory bank to fpga bitstream regression tests
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2022-05-25 11:42:32 +08:00 |
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tangxifan
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86347a9d49
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[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
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2022-05-25 11:19:49 +08:00 |
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tangxifan
|
7d694acf32
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[test] debugging basic reg test paths
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2022-05-23 11:21:36 +08:00 |
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tangxifan
|
b41cbad5d3
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[test] force to run git diff under root directory
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2022-05-23 10:32:43 +08:00 |
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tangxifan
|
488a934097
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[test] give abs path for git diff in basic regression tests
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2022-05-23 09:12:33 +08:00 |
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tangxifan
|
0dc7caf3b7
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[test] now regression test script supports remove all run dir through command-line options
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2022-05-22 13:15:39 +08:00 |
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tangxifan
|
751d87b8e3
|
[test] fix a bug in detect changes in golden netlists
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2022-05-22 13:06:47 +08:00 |
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tangxifan
|
6719a9aa26
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[test] update golden netlists/testbenches etc.
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2022-05-22 13:03:01 +08:00 |
ganeshgore
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17c4e9a1bb
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Merge branch 'master' into binder
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2022-05-10 19:58:17 -06:00 |
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tangxifan
|
d7e854eae7
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[test] deploy new test to ci
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2022-05-09 17:23:57 +08:00 |
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tangxifan
|
7ed1548c6e
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[arch] fixed a few bugs
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2022-05-09 17:22:48 +08:00 |
|
tangxifan
|
9f56e61342
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[arch] syntax
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2022-05-09 17:13:57 +08:00 |
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tangxifan
|
0afe3a6d33
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[HDL] update dff map rules to support negative triggered ffs
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2022-05-09 16:58:18 +08:00 |
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tangxifan
|
22c4d72358
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[test] add a test case to validate negative edge-triggered ff
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2022-05-09 16:57:42 +08:00 |
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tangxifan
|
9c7868cfab
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[hdl] add a counter design which is triggered by negative edges
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2022-05-09 16:41:21 +08:00 |
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tangxifan
|
812af4f722
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[arch] add arch that supports negative edge triggered flip-flop
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2022-05-09 16:32:01 +08:00 |
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tangxifan
|
c8ff3fc8dc
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[test] add regression test to validate compilation of openfpga cell library files
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2022-05-09 16:00:51 +08:00 |
|
tangxifan
|
d4992fd9ad
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[HDL] Add a multi-mode ff which can support posedge and negedge
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2022-05-09 15:52:17 +08:00 |
|
Ganesh Gore
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daae02a614
|
Minor documentation update
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2022-05-08 13:03:16 -06:00 |
|
Ganesh Gore
|
522982c9ba
|
Adde vtr_benchmarks_template for demo
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2022-05-06 22:40:36 -06:00 |
|
Ganesh Gore
|
9473523b6b
|
Added VTR arch without fracturable lut
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2022-05-06 11:05:16 -06:00 |
|
Ganesh Gore
|
275cda081e
|
[Bugfix] Typo
|
2022-05-05 08:40:21 -06:00 |
|
Ganesh Gore
|
e845b62322
|
Update regession tasks
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2022-05-05 01:46:19 -06:00 |
|
Ganesh Gore
|
1e243650b9
|
Added option to copy example projects
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2022-05-03 14:06:16 -06:00 |
|
Ganesh Gore
|
21c3dbf611
|
Added regression for template project
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2022-05-02 23:23:45 -06:00 |
|
Ganesh Gore
|
9891e42f7a
|
Added template task
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2022-05-02 11:49:16 -06:00 |
|
tangxifan
|
9bd66d531e
|
[Test] Deploy the new test case to basic regression tests
|
2022-04-13 16:06:27 +08:00 |
|
tangxifan
|
efc25aa66e
|
[Script] Fixed a bug in wrong paths
|
2022-04-13 16:04:33 +08:00 |
|
tangxifan
|
5beefda3bd
|
[Test] Add a new test case to validate the fix_pins option
|
2022-04-13 15:55:21 +08:00 |
|
tangxifan
|
576b9c2d8f
|
[Script] Disable SDC writer in multiclock examples
|
2022-03-20 11:05:29 +08:00 |
|
tangxifan
|
3e3a65223c
|
[Test] Deploy new test case to basic regression tests
|
2022-03-20 11:04:07 +08:00 |
|
tangxifan
|
f8845f7d3a
|
[Test] Add a test case to validate separated clock pins in global port
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2022-03-20 11:02:07 +08:00 |
|
tangxifan
|
c8da85cc24
|
[Doc] Update naming convention for OpenFPGA architecture files
|
2022-03-20 10:51:55 +08:00 |
|
tangxifan
|
a1e2d9c864
|
[Arch] Add a new example openfpga arch where clock ports are independent
|
2022-03-20 10:50:31 +08:00 |
|
tangxifan
|
9f7a182433
|
[Arch] Typo
|
2022-02-24 09:51:26 -08:00 |
|
tangxifan
|
fdaf97e60d
|
[Test] Update test case by using GPIO with config_done signals
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2022-02-24 09:49:34 -08:00 |
|
tangxifan
|
fcaff28e24
|
[HDL] Add a new IO cell with config_done support
|
2022-02-24 09:46:55 -08:00 |
|
tangxifan
|
a615c9d4e3
|
[Test] Rename test cases
|
2022-02-24 09:43:41 -08:00 |
|
tangxifan
|
e443a4567d
|
[Arch] Typo
|
2022-02-23 22:09:26 -08:00 |
|
tangxifan
|
b27a04eb24
|
[Test] Now test case has a config done CCFF
|
2022-02-23 22:07:11 -08:00 |
|
tangxifan
|
cf31879b20
|
[Test] Deploy new test to basic regression tests
|
2022-02-23 16:03:56 -08:00 |
|
tangxifan
|
245c7b1e45
|
[Test] Add a new test case to validate config enable signal in preconfigured testbenches
|
2022-02-23 16:02:00 -08:00 |
|
tangxifan
|
e33ba667e4
|
[Test] Add missing file
|
2022-02-20 10:59:44 -08:00 |
|
tangxifan
|
f30de1085c
|
[Test] Cover all the related testcase about bus group
|
2022-02-19 23:33:16 -08:00 |
|
tangxifan
|
b4202f52b4
|
[Test] debugging
|
2022-02-19 23:26:29 -08:00 |
|
tangxifan
|
785bb1633d
|
[Test] trying to see if we support busgroup per benchmark in task configuration file
|
2022-02-19 23:23:36 -08:00 |
|
tangxifan
|
7645d5332d
|
[Test] Update bug group examples on the big endian support
|
2022-02-18 23:09:03 -08:00 |
|
tangxifan
|
68644ea0f6
|
[Test] Add the new test to basic regression tests
|
2022-02-18 15:44:07 -08:00 |
|
tangxifan
|
f0ce1e79a3
|
[Test] Added a new test to validate bus group in full testbench
|
2022-02-18 15:43:21 -08:00 |