tangxifan
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0b74575606
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[Arch] Update arch using global reset tile port
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2021-01-09 18:04:55 -07:00 |
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tangxifan
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7b24da267a
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[Arch] Remove port size XML syntax
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2021-01-09 16:30:46 -07:00 |
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tangxifan
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9f12b25a24
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[Arch] Add port size to global port defined thru tile annotation
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2021-01-09 16:23:28 -07:00 |
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tangxifan
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0f5f0a3527
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[Arch] Add x,y coordinates to global port definition
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2021-01-09 15:50:09 -07:00 |
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tangxifan
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a14a56772a
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[Arch] Introduce new XML syntax for global port in tile annotation
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2021-01-09 15:48:42 -07:00 |
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tangxifan
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a813c9016b
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[Arch] Patch the port name in openfpga arch to avoid conflicts with OpenFPGA's reserved words
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2021-01-04 17:39:13 -07:00 |
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tangxifan
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06af30ef10
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[Test] Add test case for the SCFF usage in configuration chain
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2021-01-04 17:30:19 -07:00 |
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tangxifan
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709ee1b842
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[HDL] Update dff netlist for SCFF used in configuration chain
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2021-01-04 17:17:35 -07:00 |
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tangxifan
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c97a92d628
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[Arch] Patch openfpga architecture for ccff circuit model port requirement
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2021-01-04 17:15:50 -07:00 |
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tangxifan
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294ad97d38
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[Arch] Add openfpga architecture example using the configure-enable scan-chain flip-flop
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2021-01-04 14:56:49 -07:00 |
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tangxifan
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722a9bcf63
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[HDL] Add scan-chain DFF cell with configuration enable signal
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2021-01-04 14:31:26 -07:00 |
Lalit Sharma
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2484721a45
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Updating write_verilog_testbench by removing option explicit_port_mapping
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2020-12-22 22:17:50 -08:00 |
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Lalit Sharma
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3c9e4919b4
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Updating variable name in ys to call BLIF output file.
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2020-12-18 03:18:46 -08:00 |
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Lalit Sharma
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1f994319fd
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Adding this testcase to CI script. Also adding an option in ys script for synthesis to use openfpga compliant FF
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2020-12-16 04:19:56 -08:00 |
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Lalit Sharma
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891e2f8aa3
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Adding arch xml from SOFA repo. Also updating the script with its file location
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2020-12-16 04:14:18 -08:00 |
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Lalit Sharma
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0ee3efb306
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Adding a testcase to run yosys quicklogic flow
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2020-12-10 02:41:43 -08:00 |
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tangxifan
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6b50bbf986
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Merge pull request #134 from lnis-uofu/ganesh_dev
Support Delay Customization in OpenFPGA Task Configuration File
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2020-12-08 15:32:48 -07:00 |
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tangxifan
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6001da3a40
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[Arch] Bug fix in tileable I/O arch example
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2020-12-04 17:56:54 -07:00 |
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tangxifan
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1d0bdcfeca
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[Arch] Simplify the grid layout modeling
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2020-12-04 17:38:44 -07:00 |
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tangxifan
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1c3f625e41
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[Arch] Force empty tiles at corners for tileable I/O arch example
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2020-12-04 17:11:06 -07:00 |
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tangxifan
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0cb8457e21
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[Test] Add test case for tileable I/O
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2020-12-04 16:02:47 -07:00 |
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tangxifan
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186eb0f0a4
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[Arch] Add tileable I/O architecture example
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2020-12-04 15:59:39 -07:00 |
ganeshgore
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289d9d2169
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[Bugfix] Honors yosys_tmpl parameter in flow script
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2020-12-03 12:24:24 -07:00 |
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tangxifan
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412fb5bb31
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[Arch] Bug fix due to valid default value parser
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2020-12-02 17:51:50 -07:00 |
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tangxifan
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179b0ce304
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[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
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2020-11-30 18:11:47 -07:00 |
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tangxifan
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c7604ab94f
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[Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA
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2020-11-30 18:02:00 -07:00 |
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tangxifan
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ff53d2c375
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[HDL] Add new Scan-chain DFF cell
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2020-11-30 17:54:10 -07:00 |
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tangxifan
|
ad703ad85b
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[HDL] Add new gpio cell with protection circuitry
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2020-11-30 17:52:39 -07:00 |
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tangxifan
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27a480b5f8
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[Test] arch name fix in the test case
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2020-11-30 17:45:54 -07:00 |
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tangxifan
|
7a0a3398d4
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[Arch] Add new architecture to test global reset ports defined thru tile ports
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2020-11-30 17:43:41 -07:00 |
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tangxifan
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a1d3b439d3
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[Test] Add a new test case to define a global reset port from a global tile port
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2020-11-30 17:19:12 -07:00 |
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tangxifan
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a60bd4d14a
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[Arch] Bug fix in nature fracturable architecture
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2020-11-25 22:48:26 -07:00 |
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ganeshgore
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7db030018c
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[Bug] Fixed variable file location
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2020-11-25 22:44:40 -07:00 |
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tangxifan
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b8559249dc
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[Test] Bug fix in task configuration file
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2020-11-25 22:23:27 -07:00 |
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tangxifan
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26e4db56ad
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[Test] Add new test case for the native fracturable LUT4
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2020-11-25 22:21:23 -07:00 |
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tangxifan
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17070c6405
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[Doc] Update README in openfpga arch directory for native fracturable LUT design
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2020-11-25 22:19:20 -07:00 |
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tangxifan
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f6a667de58
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[Arch] Add openfpga architecture using native fracturable LUT
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2020-11-25 22:18:03 -07:00 |
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tangxifan
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eda671592e
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[Doc] Update README about new keyword about fracturable LUT
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2020-11-25 22:12:56 -07:00 |
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tangxifan
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0f841aa6d1
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[Arch] Add an example architecture using native fracturable LUT
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2020-11-25 22:11:14 -07:00 |
|
ganeshgore
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59bd7d0f18
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[Flow] Changed substitute to safe_sustitute option
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2020-11-25 22:09:36 -07:00 |
|
ganeshgore
|
fefba0db59
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Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
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2020-11-25 17:29:53 -07:00 |
|
ganeshgore
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1d993296d8
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[Flow] Example of using test variable in task conf
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2020-11-25 17:25:12 -07:00 |
|
ganeshgore
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1554f583b7
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[Flow] Now support explicit variable file for task
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2020-11-25 17:22:41 -07:00 |
|
tangxifan
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fd80cacaa3
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[Flow] Add example script for behaviorial verilog generation
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2020-11-22 21:14:10 -07:00 |
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tangxifan
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617f7e3062
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[Flow] disable signal initialization for behavioral verilog generation
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2020-11-22 21:13:22 -07:00 |
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tangxifan
|
5eb04e6fff
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[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals
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2020-11-22 20:53:32 -07:00 |
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tangxifan
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655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
|
348872f8a4
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[Flow] Adapt OpenFPGA shell script for the preprocessing flag option changes
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2020-11-22 16:12:28 -07:00 |
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tangxifan
|
845436fa71
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[Test] Add sequential benchmark for global tile clock test case
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2020-11-17 14:34:54 -07:00 |
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tangxifan
|
91b0dbbaa2
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[Script] Add example openfpga shell run script when using global tile clocks
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2020-11-17 14:33:12 -07:00 |