tangxifan
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c1f4a434e4
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[Doc] Update README for the regression test tasks
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2021-02-22 10:17:02 -07:00 |
tangxifan
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0384c4c61e
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Merge branch 'master' into dev
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2021-02-22 09:49:03 -07:00 |
ganeshgore
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4315660bf1
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Merge pull request #245 from lnis-uofu/dev
Throw fatal error when the number of configurable region is different between fabric key and architecture definition
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2021-02-22 09:48:23 -07:00 |
tangxifan
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d6a02a985e
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Merge pull request #248 from lnis-uofu/add_quicklogic_tests
Disabling verilog testbench generation for quicklogic tests
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2021-02-22 09:02:29 -07:00 |
Lalit Sharma
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d842026672
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Disabling verilog testbench generation for quicklogic tests
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2021-02-21 21:58:23 -08:00 |
Lalit Narain Sharma
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be5e0cdea9
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Merge pull request #241 from lnis-uofu/add_quicklogic_tests
Adding quicklogic tests and updating the corresponding conf file to r…
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2021-02-22 09:50:26 +05:30 |
Lalit Sharma
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576e6753f6
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Removing 2 more tests which are variant of and design
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2021-02-19 09:11:19 -08:00 |
Lalit Sharma
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d4c5a5655a
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Removing blif file as well as and2 testcase
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2021-02-19 08:55:17 -08:00 |
Lalit Sharma
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6de0954ca5
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Uncommenting all benchmarks except 2 that requires multiple clocks
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2021-02-19 08:40:26 -08:00 |
tangxifan
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01b9bf2a02
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[Doc] Update num_region XML for config protocol
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2021-02-18 21:58:30 -07:00 |
tangxifan
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e6091fb3ff
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[Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition
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2021-02-18 21:56:30 -07:00 |
tangxifan
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bcd8256c59
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Merge pull request #243 from lnis-uofu/dev
Bug fix for truth table creation for wired LUT created by repacking
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2021-02-18 20:44:02 -07:00 |
tangxifan
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e08ac1a41e
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[Test] Deploy synthesizable verilog test to CI
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2021-02-18 19:37:45 -07:00 |
tangxifan
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e19fc15fec
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[Test] bug fix in test case
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2021-02-18 19:37:45 -07:00 |
tangxifan
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affc8cbbc4
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[Test] Deploy test to CI
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2021-02-18 19:37:45 -07:00 |
tangxifan
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2e88b035ed
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[Test] Add wire LUT repacker test case
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2021-02-18 19:37:44 -07:00 |
tangxifan
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1f097abe99
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[Benchmark] Add micro benchmark for FIR filter
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2021-02-18 19:37:44 -07:00 |
tangxifan
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a5b8b2a64a
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[Tool] Use dedicated function to identify wire LUT created by repacker
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2021-02-18 19:37:44 -07:00 |
tangxifan
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aae03482f5
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[Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database
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2021-02-18 19:37:17 -07:00 |
ganeshgore
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122218dfd3
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Merge pull request #244 from lnis-uofu/synth_verilog_test_deployment
Deploy synthesizable verilog test to CI
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2021-02-18 10:46:19 -07:00 |
Lalit Sharma
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69cdc11ea5
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Uncommenting the tests that are running fine
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2021-02-18 04:17:12 -08:00 |
tangxifan
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a06e7e6c80
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Merge branch 'master' into dev
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2021-02-17 19:46:09 -07:00 |
tangxifan
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9004e28d47
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Merge branch 'master' into synth_verilog_test_deployment
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2021-02-17 19:45:35 -07:00 |
tangxifan
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1a23f76bd0
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Merge pull request #242 from lnis-uofu/gg_ci_cd_dev
[Bugfix] Docker regression using master regression scripts
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2021-02-17 19:21:46 -07:00 |
tangxifan
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47cb1cc2d4
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[Test] Deploy synthesizable verilog test to CI
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2021-02-17 16:13:15 -07:00 |
tangxifan
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61012897cd
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[Tool] Bug fix for truth table creation for wired LUT created by repacking algorithm
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2021-02-17 15:31:20 -07:00 |
Ganesh Gore
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808df8a87e
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[Bugfix] Docker regression using master regression scripts
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2021-02-17 13:23:45 -07:00 |
tangxifan
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d85d6e964e
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Merge pull request #227 from watcag/master
Standard-cell flow
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2021-02-17 10:11:34 -07:00 |
Lalit Sharma
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7ee01711c2
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Merge remote-tracking branch 'origin/master' into add_quicklogic_tests
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2021-02-17 00:06:59 -08:00 |
ganeshgore
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515527f7f1
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Merge pull request #238 from lnis-uofu/dev
Move regression test scripts from workflow to openfpga_flow
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2021-02-17 00:15:03 -07:00 |
Lalit Sharma
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44a979288b
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Adding quicklogic tests and updating the corresponding conf file to run them
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2021-02-16 23:08:38 -08:00 |
tangxifan
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a819375f69
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[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
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2021-02-16 16:53:13 -07:00 |
tangxifan
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2c2e493739
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[Test] Remove quicklogic test from basic tests
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2021-02-16 12:29:10 -07:00 |
tangxifan
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9c19e2b365
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[Test] Move regression test scripts from workflow to openfpga_flow
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2021-02-16 11:55:47 -07:00 |
ganeshgore
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5828e51144
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Merge pull request #237 from lnis-uofu/dev
Move quicklogic regresssion tests to a dedicated CI run
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2021-02-16 11:45:33 -07:00 |
ganeshgore
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d4ab913baa
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Merge pull request #236 from lnis-uofu/tpagarani_dev
Tpagarani dev
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2021-02-16 11:04:46 -07:00 |
tangxifan
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62bf0d0c5d
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[Test] Move quicklogic regresssion tests to a dedicated CI run
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2021-02-16 11:00:31 -07:00 |
Tarachand Pagarani
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426b6449d8
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change the test to turn off power analysis
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2021-02-15 02:45:38 -08:00 |
Tarachand Pagarani
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3a587f663a
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copy yosys output file in case power analysis setting is off
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2021-02-15 02:36:02 -08:00 |
ganeshgore
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45e8baf98f
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Merge pull request #235 from lnis-uofu/dev
Reorganize tutorial documentation
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2021-02-11 16:33:58 -07:00 |
tangxifan
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2eaec13351
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[Doc] Reorganize tutorial documentation by grouping compilation guidelines, shell setup and tool guide into a section
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2021-02-11 14:09:20 -07:00 |
tangxifan
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702bd3bbd5
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Merge pull request #231 from lnis-uofu/dev
Extended LUT Support: Now accept external LUT netlists with embedded custom logic
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2021-02-11 13:57:17 -07:00 |
tangxifan
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184788880c
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Merge pull request #224 from lnis-uofu/gg_docs
[Docs] Added documentation for docker based run and shell shortcuts documentation
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2021-02-11 09:26:29 -07:00 |
tangxifan
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c895422014
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Merge pull request #234 from lnis-uofu/bump_yosys
Bumping up latest checkins to yosys sub-module, related to adder_lut4…
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2021-02-11 09:24:49 -07:00 |
Lalit Sharma
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c495382416
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Bumping up latest checkins to yosys sub-module, related to adder_lut4 inference
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2021-02-10 22:22:58 -08:00 |
tangxifan
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e683e00032
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[HDL] Add disclaimer for the frac_lut4_arith HDL codes
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2021-02-10 14:50:11 -07:00 |
tangxifan
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1c4dc9f74b
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[Doc] Update documentation about the super LUT feature
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2021-02-10 11:49:59 -07:00 |
tangxifan
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af4cc117fb
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[Tool] bug fix in spypad lut
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2021-02-09 22:53:18 -07:00 |
tangxifan
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9b86f3bb85
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Merge branch 'master' into dev
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2021-02-09 22:40:45 -07:00 |
tangxifan
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b2984b46ee
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[Tool] Upgrade libopenfpga to support superLUT-related XML syntax
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2021-02-09 21:15:57 -07:00 |