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OpenFPGA
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1,038 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

1038 Commits

Author SHA1 Message Date
tangxifan a88263a4c2 update rr_block writer to include IPINs in XML files 2019-06-25 11:17:22 -06:00
tangxifan 785b560bd5 sorted drive_rr_nodes for RR GSBs, #. of SBs should be constant now 2019-06-24 22:46:56 -06:00
tangxifan fd301eeb66 many bug fixing and now start improving the routability of tileable rr_graph 2019-06-24 17:33:29 -06:00
tangxifan 0d62661c71 bug fixing and spot critical bugs in directlist parser 2019-06-23 20:52:38 -06:00
tangxifan cdd4af9c58 vpr likes the tileable rr_graph while fpga_x2p does not 2019-06-23 18:11:13 -06:00
tangxifan 59df305668 bug fixing and reorganize rr_graph builder source files 2019-06-23 16:40:13 -06:00
tangxifan 2837f44df2 bug fixing for tileable rr_graph generator. 2019-06-22 20:41:06 -06:00
tangxifan 7c38b32eb1 keep bug fixing for tileable rr_graph generator 2019-06-21 22:51:11 -06:00
tangxifan 1b91c32121 Merge branch 'multimode_clb' into tileable_routing 2019-06-21 17:59:55 -06:00
tangxifan 41954056ce many bug fixing for tileable rr_graph generator. Still debugging 2019-06-21 17:58:46 -06:00
AurelienUoU 0a42f6a796 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-21 15:47:14 -06:00
AurelienUoU c0d7099cd6 Allow CB on top of blocks with height > 1 2019-06-21 15:46:05 -06:00
tangxifan d48fd959a9 keep bug fixing for tileable rr_graph generator 2019-06-20 22:30:26 -06:00
tangxifan 548242b368 plug-in tileable rr generator which can be enable by a XML property 2019-06-20 21:06:26 -06:00
tangxifan cf82d87e11 Merge branch 'multimode_clb' into tileable_routing 2019-06-20 18:18:20 -06:00
tangxifan baab9c4a21 basically finished the coding of tileable rr_graph generator. testing to go 2019-06-20 18:17:07 -06:00
Baudouin Chauviere be25b6dd66 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-20 14:11:03 -06:00
Baudouin Chauviere 3bd6c40a10 Report timing modified to have only one liners 2019-06-20 14:10:39 -06:00
AurelienUoU a7502bb43b Avoid configuration bits for module wihch don't require them 2019-06-20 09:40:41 -06:00
tangxifan e7f2bd3b7c Merge branch 'multimode_clb' into tileable_routing 2019-06-19 21:31:54 -06:00
tangxifan 2f15d2d13c keep developing tileable rr_graph, track2ipin and opin2track to go 2019-06-19 21:30:16 -06:00
AurelienUoU ff00e4c79c Free only if it's possible to free 2019-06-19 16:15:30 -06:00
tangxifan ba15358564 developing ipin2track mapping for tiles 2019-06-18 18:06:21 -06:00
tangxifan 9ca1b42f4c developing switch block pattern for tileable routing architecture 2019-06-18 16:52:42 -06:00
tangxifan 352c97302b start building object GSB graph 2019-06-17 22:10:30 -06:00
tangxifan f4191315da use rr_gsb to build edges of rr_graph 2019-06-17 18:01:45 -06:00
tangxifan 51ff150a77 bug fixing in tileable rr_graph generator 2019-06-17 10:16:08 -06:00
tangxifan 0d14fef53e bug fixing in setting CHANX and CHANY nodes in tileable rr_graph generator 2019-06-16 23:02:18 -06:00
tangxifan 04ffb99ca6 Merge branch 'multimode_clb' into tileable_routing 2019-06-16 16:01:30 -06:00
Baudouin Chauviere 57a4ad1f99 Break memories even in the clb sdc 2019-06-16 14:27:29 -06:00
tangxifan 1af3b5ef55 set chan_rr_nodes in tileable rr_graph builder 2019-06-16 14:23:19 -06:00
tangxifan 8c9cc003ea developing routing track rr_node set up in tileable routing architecture 2019-06-15 18:11:08 -06:00
tangxifan 28f54961b2 Merge branch 'multimode_clb' into fpga_spice 2019-06-15 15:37:26 -06:00
Xifan Tang 155c8d4924 fix CMakeList bug in disabling VPR graphics 2019-06-15 13:21:25 -06:00
tangxifan 18c355d3ee Merge branch 'multimode_clb' into tileable_routing 
Conflicts:
	vpr7_x2p/vpr/regression_verilog.sh
 2019-06-15 12:27:40 -06:00
tangxifan b9feaf0eeb fix conflicts on the regression.sh 2019-06-15 12:26:37 -06:00
tangxifan d19b470b33 Merge branch 'tileable_routing' into multimode_clb 
Conflicts:
	vpr7_x2p/vpr/regression_verilog.sh
 2019-06-15 12:25:30 -06:00
tangxifan c8bf456097 bug fixing for memory leaking in allocating pb_rr_graph and power estimation 2019-06-15 12:23:36 -06:00
tangxifan d3296d0975 developing tileable rr_graph builder 2019-06-14 22:35:42 -06:00
tangxifan a33627606e developing tileable routing track arrangement 2019-06-14 17:35:40 -06:00
AurelienUoU 29dadc51b4 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-14 11:46:02 -06:00
AurelienUoU c76dbaac33 Update regression test avoiding overwritting files 2019-06-14 11:44:44 -06:00
tangxifan 4d2a3680be support bus explicit port mapping to standard cells (for BRAMs) 2019-06-14 11:09:15 -06:00
tangxifan 0902d1e75a c++ string is not working, use char which is stable 2019-06-13 18:38:46 -06:00
tangxifan 5f61cd8876 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 
Conflicts:
	vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
 2019-06-13 16:32:39 -06:00
tangxifan af1628abfe use bus port for primitives in Verilog generator 2019-06-13 16:26:58 -06:00
tangxifan dddbbac85c merge from multimode_clb bug fixing 2019-06-13 15:59:34 -06:00
tangxifan e86874adca Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into fpga_spice 2019-06-13 15:54:27 -06:00
AurelienUoU 15b4cc9ecb Error correction in memory generation for pb_types without modes 2019-06-13 15:34:25 -06:00
tangxifan 43128ad3f0 fix a bug in formal verification port for memory bank configuration circuits 2019-06-13 15:33:13 -06:00