tangxifan
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91a2dc4fd7
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Merge pull request #340 from lnis-uofu/opt_signal_init
Signal initialization HDL codes will not be outputted unless specified in the command-line option
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2021-06-24 19:28:57 -06:00 |
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tangxifan
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67dec810eb
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[Tool] Remove icarus simulator flag; Reduce the file size of preconfigured fabric wrapper by only output the necessary force/deposit HDL codes
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2021-06-24 17:27:32 -06:00 |
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tangxifan
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549657e1fb
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[Tool] Remove out-of-date flag: INITIAL_SIMULATION from code base
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2021-06-24 17:13:36 -06:00 |
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tangxifan
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5364d8104f
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[Tool] Add signal_init option to preconfigured fabric wrapper writer
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2021-06-24 17:07:41 -06:00 |
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tangxifan
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779437cd37
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[Doc] Update documentation to remove out-of-date options related to signal_init
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2021-06-24 17:07:15 -06:00 |
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tangxifan
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21d1519658
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[Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option
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2021-06-24 16:56:28 -06:00 |
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tangxifan
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c1dab21686
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Merge pull request #269 from lnis-uofu/dev
Patch wrong paths in FPGA-SDC
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2021-06-23 10:39:33 -06:00 |
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tangxifan
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ce3c80f499
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Merge branch 'master' into dev
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2021-06-23 09:15:03 -06:00 |
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tangxifan
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4ca805b5d5
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Merge pull request #337 from lnis-uofu/write_io_mapping
Write io mapping
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2021-06-22 18:55:51 -06:00 |
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tangxifan
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4fa745caa8
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Merge branch 'master' into write_io_mapping
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2021-06-22 17:42:15 -06:00 |
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tangxifan
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931dc21687
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Merge pull request #339 from lnis-uofu/micro_benchmark
Micro benchmark
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2021-06-22 17:42:03 -06:00 |
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tangxifan
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b2c30e3103
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[Test] Bug fix in mcnc openfpga shell script
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2021-06-22 16:40:24 -06:00 |
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tangxifan
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e34fbf8ecf
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[Test] Deploy MCNC big20 to the micro benchmark regression test
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2021-06-22 16:36:04 -06:00 |
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tangxifan
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f06017581c
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[Test] Bug fix in counter micro benchmark tests
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2021-06-22 16:33:50 -06:00 |
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tangxifan
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0a0d10b36d
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[HDL] Bug fix in Verilog syntax
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2021-06-22 16:18:46 -06:00 |
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tangxifan
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4421dfcbbd
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Merge branch 'master' into micro_benchmark
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2021-06-22 14:29:29 -06:00 |
ganeshgore
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cbcf41062f
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Merge pull request #338 from lnis-uofu/openfpga_flow_dir_name
Support benchmarks with same top module names in openfpga flow script
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2021-06-22 11:28:15 -07:00 |
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tangxifan
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fd580bb36f
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[Script] Update script to keep back compatibility: local run directory is different only for those benchmarks sharing the same top module name
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2021-06-22 11:45:23 -06:00 |
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tangxifan
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260b14c3d4
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[CI] Add the micro benchmark regression test to CI
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2021-06-21 18:37:42 -06:00 |
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tangxifan
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0b2d6eb147
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[Test] Add micro benchmark to a dedicated regression test
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2021-06-21 18:35:41 -06:00 |
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tangxifan
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760570d883
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[Test] Update counter test case for cover most counter HDL design
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2021-06-21 18:13:18 -06:00 |
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tangxifan
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9c24a739be
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[Test] Added a MAC benchmark sweeping test
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2021-06-21 17:40:53 -06:00 |
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tangxifan
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07dcf3ad27
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[HDL] Add more micro benchmarks for counter, and-gate and mac unit
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2021-06-21 16:48:35 -06:00 |
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tangxifan
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f9e66e1bae
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[Script] Support benchmarks with same top module names in openfpga flow script; Now each benchmark local run directory has a unique name;
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2021-06-21 15:27:12 -06:00 |
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tangxifan
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74d8e02b33
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Merge branch 'master' into write_io_mapping
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2021-06-18 16:28:44 -06:00 |
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tangxifan
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cbbf601edc
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[Tool] Fix a compiler warning due to uninitialized data structure
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2021-06-18 16:20:13 -06:00 |
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tangxifan
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fed975c52a
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[Tool] Add postfix removal support in write_io_mapping command
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2021-06-18 16:13:50 -06:00 |
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ganeshgore
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70a4dc26d4
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Merge pull request #335 from lnis-uofu/openfpga_flow_patch
Openfpga flow script outputs detailed error message when task directory is not found
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2021-06-18 12:01:58 -06:00 |
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tangxifan
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fce84e564d
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[Script] Patch on missing string to show in error message
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2021-06-18 11:20:35 -06:00 |
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tangxifan
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0e01177cf0
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[Script] Now openfpga flow script output detailed error message when task is not found
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2021-06-18 11:01:45 -06:00 |
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tangxifan
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a07859b567
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Merge pull request #334 from lnis-uofu/tangxifan-patch-1
Update fix_device_route_chan_width_example_script.openfpga
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2021-06-18 10:37:38 -06:00 |
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tangxifan
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96cb3081ab
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Update fix_device_route_chan_width_example_script.openfpga
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2021-06-18 09:51:16 -06:00 |
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tangxifan
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b16de387f9
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Merge pull request #331 from lnis-uofu/tutorials
Adding tutorial video and updating several pages to fix grammar and spelling
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2021-06-16 14:47:02 -06:00 |
bbleaptrot
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de550ac550
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Merge branch 'master' into tutorials
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2021-06-16 14:00:31 -06:00 |
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bbleaptrot
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7787fe9795
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update reference to match doc page
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2021-06-16 12:46:43 -06:00 |
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bbleaptrot
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858bb2f21e
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fix mistake in first line of page
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2021-06-16 12:45:04 -06:00 |
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bbleaptrot
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624e9f3bb7
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Update notation at top to match pages in doc
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2021-06-16 12:44:01 -06:00 |
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bbleaptrot
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ece6e92f06
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Add video at top of page
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2021-06-16 12:29:17 -06:00 |
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tangxifan
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36113d35ac
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Merge pull request #328 from lnis-uofu/testbench_external_bitstream
Support ``default_net_type`` customization in Verilog testbench generator
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2021-06-14 17:45:14 -06:00 |
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bbleaptrot
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7a303463c3
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Update shell_shortcuts.rst
Update grammar. <_openfpga_task_args> no longer works
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2021-06-14 15:34:13 -06:00 |
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bbleaptrot
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5e8b5d641f
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Update compile.rst
update grammar
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2021-06-14 14:51:19 -06:00 |
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bbleaptrot
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1a2ced678e
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Update tech_highlights.rst
Update grammar and add link to standard_cell_library tutorial
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2021-06-14 14:34:12 -06:00 |
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bbleaptrot
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d0549f10b3
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Make a :ref: for tutorial
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2021-06-14 14:28:21 -06:00 |
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tangxifan
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164baee8bc
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Merge branch 'master' into testbench_external_bitstream
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2021-06-14 14:06:37 -06:00 |
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tangxifan
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9585e1d3b5
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[Doc] Update documentation about 'default_net_type' option in testbench generators
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2021-06-14 14:00:34 -06:00 |
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bbleaptrot
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dc13325639
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Update motivation.rst
Fixing grammar and spacing
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2021-06-14 13:44:20 -06:00 |
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tangxifan
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d40cf98c48
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[Test] Update test cases by using default net type in testbench generator
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2021-06-14 11:47:28 -06:00 |
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tangxifan
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d9d57aad42
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[Tool] Added default net type options to verilog testbench generator command
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2021-06-14 11:37:49 -06:00 |
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tangxifan
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24e6d31016
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Merge pull request #326 from lnis-uofu/testbench_external_bitstream
Create new commands in place of the multi-functional ``write_verilog_testbench`` command
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2021-06-09 19:01:54 -06:00 |
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tangxifan
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7ade48343c
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[Tool] Deprecate command 'write_verilog_testbench'
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2021-06-09 17:06:01 -06:00 |