Commit Graph

6395 Commits

Author SHA1 Message Date
tangxifan b330fb4bb7 Add Travis support for Mac OS Mojave 2019-04-10 11:51:12 +08:00
BaudouinChauviere cb34ac0243
Update sc_flow.rst 2019-04-01 16:30:31 -06:00
BaudouinChauviere 361bbc13e3
Update func_verify.rst 2019-04-01 16:29:42 -06:00
BaudouinChauviere a176bf3a19
Update file_organization.rst 2019-04-01 16:28:48 -06:00
BaudouinChauviere 01371ce54d
Update customize_subckt.rst 2019-04-01 16:27:06 -06:00
BaudouinChauviere 1ea7ec3265
Update spice_simulation.rst 2019-04-01 16:26:02 -06:00
BaudouinChauviere cfdc072164
Update file_organization.rst 2019-04-01 16:25:09 -06:00
BaudouinChauviere fcc3bf0967
Update command_line_usage.rst 2019-04-01 16:23:24 -06:00
BaudouinChauviere f4b72bd4e1
Update link_circuit_modules.rst 2019-04-01 16:21:59 -06:00
BaudouinChauviere ce300c196c
Update circuit_modules.rst 2019-04-01 16:13:23 -06:00
BaudouinChauviere 6e065ef3b3
Update tech_lib.rst 2019-04-01 16:09:31 -06:00
BaudouinChauviere aed779ca3d
Update spice_sim_setting.rst 2019-04-01 16:08:00 -06:00
BaudouinChauviere 4900caaed9
Update generality.rst 2019-04-01 16:04:17 -06:00
BaudouinChauviere 33df25366c
Update eda_flow.rst
Correction fix
2019-04-01 16:02:47 -06:00
BaudouinChauviere d6261f1f59
Update motivation.rst
Typo and better explanations correction
2019-04-01 15:57:04 -06:00
Baudouin Chauviere 39f7b0b9a2 Update of the doc for better fit with the current version 2019-04-01 11:55:28 -06:00
Baudouin Chauviere c4b42726c4 fixes easing thehandling by the user. 2019-03-31 07:55:05 -06:00
tangxifan b06df18a89
Update rr_graph_area.c 2019-03-11 21:46:42 +08:00
AurelienUoU 213f94ddee Correct preconfiguration 2019-01-31 16:43:47 -07:00
tangxifan 5e36aa82c5 fixa bug in determining mux structure 2019-01-22 13:54:50 -07:00
Baudouin Chauviere 32d1132bf8 Addition of the dependencies in the documentation of the compilation 2019-01-10 23:28:48 -07:00
BaudouinChauviere 3ca23f2026
Update macos_compilation.md 2019-01-10 22:04:10 -08:00
BaudouinChauviere a904e4a37b
Update red_hat_compilation.md 2019-01-10 22:03:55 -08:00
BaudouinChauviere 568a5a0e92
Update ubuntu_compilation.md 2019-01-10 22:03:37 -08:00
Baudouin Chauviere f3e7ae0823 Hot fix 2019-01-10 17:37:15 -07:00
tangxifan b8187bbca5 fix a bug for supporting default circuit_model of LUTs and FFs 2019-01-10 15:10:05 -07:00
Baudouin Chauviere 9c8444da43 update of the examples supplied to get the right paths 2019-01-10 00:06:20 -07:00
Baudouin Chauviere 4ae3aa517c go.sh replaces the paths now 2019-01-09 23:16:43 -07:00
Baudouin Chauviere 510c27f816 Removed commercial scripts, replaced by academia ones 2019-01-09 11:56:07 -07:00
Baudouin Chauviere 3b4fc16c60 Adding help message on the go.sh 2019-01-09 11:54:28 -07:00
tangxifan 66701838ff update relative path in ARCH XML 2019-01-08 11:41:24 -07:00
AurelienUoU b80e435548 Correct manual testbench generation bug 2019-01-07 18:03:56 -07:00
BaudouinChauviere 5dbcfa6d70
Repair broken link 2019-01-03 18:26:30 +01:00
BaudouinChauviere 28010f6c91
Testing another link method 2019-01-03 18:24:06 +01:00
Laboratory for Nano Integrated Systems (LNIS) 30f2ada557
Repaired broken links 2019-01-03 18:18:03 +01:00
tangxifan 349e634fef
Update README.md 2018-12-30 14:37:17 -07:00
tangxifan 9f3da4d1a5
Update README.md 2018-12-30 14:35:07 -07:00
LNIS-Projects 77dd7f3e04
correction of the name of the figure 2018-12-29 01:45:45 +01:00
LNIS-Projects 0f6ac32f43
Further resizing 2018-12-29 01:44:24 +01:00
LNIS-Projects 38a3b01520
Resize the images 2018-12-29 01:42:43 +01:00
Baudouin Chauviere 9ee50de26a Adding information on the layout 2018-12-29 01:14:26 +01:00
Baudouin Chauviere 0a5391c14f Addition of some illustrations 2018-12-26 18:16:16 +01:00
LNIS-Projects de7d646fa0
Update func_verify.rst
Functional Verification documentation
2018-12-26 18:05:24 +01:00
LNIS-Projects c0626e9a1c
Adding the Verification Step from ModelSim 2018-12-26 18:00:03 +01:00
AurelienUoU 7ff245448b Add new benchmark and modify go.sh to use it 2018-12-26 04:24:26 -07:00
LNIS-Projects c506e16d33
Update command_line_usage.rst
Small fix
2018-12-22 14:46:15 +01:00
LNIS-Projects ba303450e2
Update file_organization.rst 2018-12-22 14:45:00 +01:00
LNIS-Projects 5fa6c84087
New fpga_verilog commands documented 2018-12-22 14:39:51 +01:00
LNIS-Projects 41067f6ac1
Update .travis.yml 2018-12-14 16:13:05 -07:00
Robert Weischedel 1b6d5b3b5d
Update .travis.yml 2018-12-14 15:30:25 -07:00