tangxifan
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9f56e61342
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[arch] syntax
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2022-05-09 17:13:57 +08:00 |
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tangxifan
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812af4f722
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[arch] add arch that supports negative edge triggered flip-flop
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2022-05-09 16:32:01 +08:00 |
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tangxifan
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f8ef3df560
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[Test] Now use 4x4 fabric in testing write_rr_gsb commands
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2022-01-26 11:41:48 -08:00 |
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tangxifan
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27caeb1d1f
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[Arch] Patched VPR arch
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2022-01-02 20:47:22 -08:00 |
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tangxifan
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384a1e58d6
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[Arch] Patch architecture using DSP with registers
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2022-01-02 20:44:43 -08:00 |
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tangxifan
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e3baec63f8
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[Arch] Bug fix on architecture with registerable DSP
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2022-01-02 20:35:48 -08:00 |
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tangxifan
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f667065f75
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[Arch] Bug fix in DSP with registers architecture
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2022-01-02 20:34:26 -08:00 |
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tangxifan
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9c476ed5db
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[Arch] Syntax error fix
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2022-01-02 20:27:00 -08:00 |
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tangxifan
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7598455497
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[Doc] Update naming convention for architecture files
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2022-01-02 19:51:09 -08:00 |
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tangxifan
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48491fcf52
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[Flow] Add example architecture for DSP with input and output registers
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2022-01-02 19:47:39 -08:00 |
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tangxifan
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81966c2131
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[Doc] Update README for DSP blocks
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2022-01-02 18:27:37 -08:00 |
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tangxifan
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be47e78289
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[Arch] Change arch for Sapone test
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2021-10-30 15:23:19 -07:00 |
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tangxifan
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dcb89cb16b
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[Arch] Patch architecture due to missing mode bit definition
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2021-07-02 11:41:29 -06:00 |
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tangxifan
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fd85f956c9
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[Arch] Update k4n4 arch with true multi-mode flip-flop
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2021-07-02 11:08:39 -06:00 |
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tangxifan
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bc34efe337
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[Arch] Bug fix in the architecture using BRAM spanning two columns
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2021-04-28 14:32:17 -06:00 |
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tangxifan
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be98775ae5
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[Arch] Reduce the size of DPRAM in example architecture to accelerate testing
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2021-04-28 10:45:10 -06:00 |
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tangxifan
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79b27a6329
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[Arch] Patch arch using DPRAM block with wide = 2
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2021-04-28 10:29:09 -06:00 |
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tangxifan
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834657f2da
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[Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes
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2021-04-27 23:41:14 -06:00 |
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tangxifan
|
0f8aaae2bc
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[Arch] Patch architecture using 16kbit dual port RAM
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2021-04-27 19:54:34 -06:00 |
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tangxifan
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8c007c7c49
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[Arch] Add a new example architecture where a DSP block occupies a 2x2 grid
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2021-04-26 16:28:10 -06:00 |
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tangxifan
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7d4c5e3cd1
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[Arch] Patch pin location of dsp8 to be evenly placed on the right side of a height=2 block
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2021-04-26 12:00:57 -06:00 |
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tangxifan
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6e87b8875b
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[Arch] Patch the pin location of frac dsp16 to appear on the top side of a height=2 block
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2021-04-26 11:59:25 -06:00 |
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tangxifan
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5adffad602
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[Arch] Changes to the arch to avoid a bug where the rr_nodes at top side of a heterogenenous block have no fan-in!!!
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2021-04-24 15:49:53 -06:00 |
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tangxifan
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4f454abfde
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[Arch] Add a new architecture using fracturable 16-bit DSP blocks
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2021-04-24 14:01:42 -06:00 |
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tangxifan
|
ce6018e123
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[Arch] Enriched DFF model to support active-low/high FFs
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2021-04-21 22:48:31 -06:00 |
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tangxifan
|
9d9840d9b7
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[Arch] Add architecture using multi-mode DFFs
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2021-04-21 19:49:48 -06:00 |
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tangxifan
|
e3dafe99da
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[Arch] Revert to old version arch due to editing by mistake
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2021-04-16 20:58:32 -06:00 |
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tangxifan
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16e02ef485
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[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
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2021-04-16 20:47:39 -06:00 |
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tangxifan
|
4239bb4e68
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[Arch] Patch architecture files using multi-mode DFFs
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2021-04-16 19:59:55 -06:00 |
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tangxifan
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f2f7f010ea
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[Arch] Add new architectures using DFF with reset in VPR
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2021-04-16 19:26:18 -06:00 |
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tangxifan
|
64294ae4eb
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[Doc] Update README for architecture files due to new architecture features
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2021-04-16 19:25:54 -06:00 |
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tangxifan
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44d97ead86
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Merge branch 'master' into hetergeneous_arch
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2021-03-23 17:05:03 -06:00 |
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tangxifan
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fdec72b5bc
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[Arch] Add an example architecture with 8-bit single-mode multiplier
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2021-03-23 15:35:06 -06:00 |
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tangxifan
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911979a731
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[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
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2021-03-20 18:04:59 -06:00 |
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tangxifan
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910f8471dd
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[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
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2021-03-17 15:10:05 -06:00 |
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tangxifan
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ad25944e59
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[Arch] Patched superLUT architecture example when trying adder8 synthesis script
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2021-02-23 19:00:27 -07:00 |
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tangxifan
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ca135f3325
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[Arch] Add flagship architecture with 8-clock
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2021-02-22 15:01:18 -07:00 |
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tangxifan
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1c09c55e9f
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[Arch] Add hetergenenous 8-clock FPGA architecture
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2021-02-22 13:38:50 -07:00 |
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tangxifan
|
0ac75723af
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[Arch] Add new architecture with 8 clocks
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2021-02-22 11:00:45 -07:00 |
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tangxifan
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b9c2564a7e
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[Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks
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2021-02-22 10:49:21 -07:00 |
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tangxifan
|
7dcc14d73f
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[Arch] Bug fix in the example arch with super LUT
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2021-02-09 15:52:22 -07:00 |
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tangxifan
|
304b26c97f
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[Arch] Add example architectures for superLUT circuit model
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2021-02-09 15:11:12 -07:00 |
AurelienAlacchi
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00fc3d7622
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Merge pull request #217 from lnis-uofu/dev
Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
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2021-02-05 09:53:28 -07:00 |
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tangxifan
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dc09c47411
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[Arch] Remove packable from architecture files and replace with disable_packing
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2021-02-04 18:03:56 -07:00 |
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tangxifan
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66bc370c4d
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[Arch] Use disable_packing in architecture library
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2021-02-04 16:29:03 -07:00 |
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tangxifan
|
a4c266d59a
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[Arch] Add pack patterns for soft adders; Still fail in packing
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2021-02-03 19:11:15 -07:00 |
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tangxifan
|
cac1160bf7
|
[Arch] Patch QLSOFA architecture to support carry chain pattern; Still buggy for VPR packer; Looking for a solution
|
2021-02-03 11:20:56 -07:00 |
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tangxifan
|
021520783b
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[Arch] Add dummy timing info to adder_lut4 and carry_follower model
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2021-02-02 15:49:43 -07:00 |
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tangxifan
|
10302752a7
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[Arch] Bug fix in architecture. Now soft adder modes are accepted
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2021-02-01 13:43:39 -07:00 |
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tangxifan
|
d8927e12e8
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[Arch] Add soft adder operating mode to test architecture
|
2021-02-01 12:25:37 -07:00 |