AurelienUoU
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ba05a08ef0
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Path correction in tech debugging + correction of yosys rewrite file in fpga_flow
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2019-05-30 09:52:19 -06:00 |
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AurelienUoU
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f934f6f0a3
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Debug step
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2019-05-28 15:01:16 -06:00 |
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AurelienUoU
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e0717369e1
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Re-insert power option in regression test
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2019-05-28 09:48:03 -06:00 |
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AurelienUoU
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d3f0ab59c2
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Remove -power token until option is fixed
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2019-05-23 19:26:25 -06:00 |
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AurelienUoU
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3811c18953
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Correct syntax error in tokens of regression_fpga_flow.sh
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2019-05-23 18:33:47 -06:00 |
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AurelienUoU
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1018134726
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Update yosys to latest version + add simulation in fpga_flow
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2019-05-23 17:55:49 -06:00 |
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AurelienUoU
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2b04376209
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Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks
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2019-05-22 13:44:48 -06:00 |
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AurelienUoU
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b4c97f86a3
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Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches
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2019-05-21 17:24:06 -06:00 |
tangxifan
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d10e05f5cc
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-21 12:16:33 -06:00 |
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tangxifan
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ec3b4c86c4
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update file organization and be ready for SB/CB class
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2019-05-21 12:15:38 -06:00 |
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AurelienUoU
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199cd99b23
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Add dummy clock name in ace2 commands
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2019-05-21 10:35:12 -06:00 |
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AurelienUoU
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2392d11790
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Add debug command to understandn travis issue with ace
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2019-05-20 16:06:37 -06:00 |
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AurelienUoU
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becb90cd16
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Correct syntax error in ace2 log file generation
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2019-05-20 13:56:50 -06:00 |
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AurelienUoU
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fbebb45bf2
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Path correction in config file
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2019-05-20 11:13:30 -06:00 |
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AurelienUoU
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82c76a2c39
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Test removing the shell specification in fpga_flow.pl
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2019-05-20 10:35:33 -06:00 |
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AurelienUoU
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43a64c26e8
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Change tcsh to csh in fpga_flow.pl -> tcsh not found by travis
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2019-05-20 09:44:38 -06:00 |
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AurelienUoU
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17ad905b14
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Update flow and allow netlist generation
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2019-05-17 17:00:38 -06:00 |
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AurelienUoU
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df8bb0db1a
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Add MCNC Benchmarks netlists generation to travis regression test
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2019-05-17 15:22:04 -06:00 |
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AurelienUoU
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ff9b84d800
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Bug fix in Icarus requirement
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2019-05-10 14:07:32 -06:00 |
Baudouin Chauviere
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79f3db9880
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removed the now useless tutorial part
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2018-12-10 13:57:01 -07:00 |
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tangxifan
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72fbd8d6a8
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update blif reader to identify clock signals
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2018-12-10 13:28:44 -07:00 |
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Baudouin Chauviere
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79930982cf
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Changed for the naming
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2018-12-08 16:19:38 -07:00 |
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tangxifan
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b3c1018e28
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fixed a bug in wired LUT
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2018-12-06 16:50:30 -07:00 |
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Baudouin Chauviere
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0b1ccf7722
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and in the config path as well
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2018-12-06 14:57:32 -07:00 |
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Baudouin Chauviere
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fe47b3d21f
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Changing arch from memory dec to scff. Get the bitstream from go.sh
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2018-12-06 14:03:17 -07:00 |
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tangxifan
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4f5f8de46f
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Add Yosys and update flow_flow Perl Script
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2018-11-30 21:14:43 -07:00 |
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Baudouin Chauviere
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d55ecd154b
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Add the PTM to the benchmark flow
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2018-11-21 11:32:34 -07:00 |
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Baudouin Chauviere
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8ce0a84bc1
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Correction of the global make, the fpga_flow and the doc
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2018-11-20 14:47:15 -07:00 |
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Baudouin Chauviere
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03e902023a
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Perl script integrated to flow. rm shell one
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2018-11-20 13:32:11 -07:00 |
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Baudouin Chauviere
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15d69e2bb1
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Generation script finished TODO: integration in flow
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2018-11-20 13:24:31 -07:00 |
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Baudouin Chauviere
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e74f05a161
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Switching from sh to pl
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2018-11-20 10:15:31 -07:00 |
Baudouin Chauviere
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9611576d6a
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Update on the examples to respect the new syntax
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2018-11-19 15:50:29 -07:00 |
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Baudouin Chauviere
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dddca8acbb
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Global Makefile and typo correction
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2018-10-24 17:34:51 -06:00 |
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Baudouin Chauviere
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9538dbd644
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Config script written and changed some rights for some files
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2018-10-24 15:59:32 -06:00 |
Aurelien Alacchi
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e0c2fc2c8a
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Documentation_code&example_update
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2018-10-12 15:50:09 -06:00 |
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Baudouin Chauviere
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e5c6471fc2
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Update of the Readme and added an example
ReadMe is now cleaner
|
2018-10-03 17:10:29 -06:00 |
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Baudouin Chauviere
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4a4f539365
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Change rights script
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2018-09-27 15:51:09 -06:00 |
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Baudouin Chauviere
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665678267d
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Change rights script
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2018-09-27 15:17:48 -06:00 |
Xifan Tang
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1cf066d3ad
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Fixing minor bugs
|
2018-09-06 14:25:23 -06:00 |
|
Xifan Tang
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c009a37580
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fix minor bugs
|
2018-09-04 17:56:37 -06:00 |
|
Xifan Tang
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42da9160f0
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Clean codes and update
|
2018-09-04 17:49:20 -06:00 |
|
Xifan Tang
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00ecd0bb1d
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Cleanup codes and organization
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2018-09-04 17:31:30 -06:00 |
|
Xifan Tang
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cb15bb5082
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Clean code and fix minor bugs
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2018-08-10 13:46:00 -06:00 |
|
Xifan Tang
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b0ef554b35
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Add power property XML
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2018-08-09 11:27:36 -06:00 |
|
Xifan Tang
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90669d19c5
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Update FPGA-SPICE and flow configurations
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2018-08-09 11:27:16 -06:00 |
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Xifan Tang
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fe13168f8f
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Add ABC and ACE2, fix bugs for fpga_flow and VPR
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2018-07-27 22:54:52 -06:00 |
|
Xifan Tang
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158dec405e
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Reorganize the code directory
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2018-07-26 11:28:21 -06:00 |