tangxifan
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712eeb1340
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bring bitstream generator for routing modules online
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2020-02-23 22:09:46 -07:00 |
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tangxifan
|
86c7c24701
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add fabric bitstream generation online
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2020-02-23 20:58:17 -07:00 |
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tangxifan
|
8723007f68
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Bring mux bitstream generation online
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2020-02-23 20:53:24 -07:00 |
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tangxifan
|
51439ba3b4
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add bitstream writer to be integrated
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2020-02-23 20:40:18 -07:00 |
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tangxifan
|
2d17395e13
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start integrating fpga_bitstream. Bring data structures online
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2020-02-22 23:04:42 -07:00 |
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tangxifan
|
9583731531
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add results saver for lb router
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2020-02-22 22:10:32 -07:00 |
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tangxifan
|
921bf7dd7b
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use constant in device annotation
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2020-02-21 20:45:22 -07:00 |
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tangxifan
|
926e429374
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add save repacking results in physical pb
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2020-02-21 20:39:49 -07:00 |
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tangxifan
|
12f2888c7c
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add physical pb data structure and basic allocator
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2020-02-21 17:47:27 -07:00 |
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tangxifan
|
b035b4c87f
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debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
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2020-02-21 12:16:50 -07:00 |
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tangxifan
|
1b66e837ba
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bug fixing for lb router. Add physical mode to default node expanding settings
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2020-02-21 11:29:00 -07:00 |
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tangxifan
|
0b0e00b5f4
|
debugging the LbRouter
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2020-02-20 21:56:15 -07:00 |
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tangxifan
|
4abaef14b5
|
bug fixed in pb_pin fix-up. This is due to A CRITICAL BUG IN PHYSICAL_TILE PIN MAPPING!!!
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2020-02-20 20:50:59 -07:00 |
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tangxifan
|
3e07d7d5e0
|
finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
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2020-02-20 20:26:20 -07:00 |
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tangxifan
|
fdb27c5a6b
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move lb_rr_graph construction to repack command
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2020-02-20 13:24:34 -07:00 |
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tangxifan
|
d8ab5536e1
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add advanced check codes for lb_rr_graph
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2020-02-19 21:41:05 -07:00 |
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tangxifan
|
ed5d83178f
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add fundamental check codes for LbRRGraph
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2020-02-19 21:07:31 -07:00 |
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tangxifan
|
bc27f9dd0c
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add check codes for nets inside LbRouter
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2020-02-19 20:34:30 -07:00 |
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tangxifan
|
43f15e4d6f
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add methods to LbRouter for nets to be routed and access to routing traceback
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2020-02-19 16:40:53 -07:00 |
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tangxifan
|
444b994285
|
flatten the t_net inside LbRouter into internal data
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2020-02-19 15:37:22 -07:00 |
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tangxifan
|
2b37fcb296
|
use strong id for nets to be routed in LbRouter
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2020-02-19 15:09:25 -07:00 |
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tangxifan
|
2f1bcdd27d
|
use local data to store illegal modes for pb_graph_node inside LbRouter
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2020-02-19 14:53:35 -07:00 |
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tangxifan
|
5ccb4adb08
|
refactored LB router main function
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2020-02-19 11:09:24 -07:00 |
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tangxifan
|
3d5a15d41e
|
refactored most functions except echo and try_route() in LbRouter
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2020-02-19 00:07:36 -07:00 |
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tangxifan
|
80fa6f8a0a
|
refactored skip nets in LbRouter
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2020-02-18 22:08:51 -07:00 |
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tangxifan
|
289c869caf
|
refactored expand rt_node in LbRouter
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2020-02-18 22:01:22 -07:00 |
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tangxifan
|
c7ef14fc23
|
refactoring node expansion in LbRouter
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2020-02-18 21:51:03 -07:00 |
|
tangxifan
|
11879d43b4
|
add methods one by one to LbRouter from cluster_router.cpp
|
2020-02-18 19:22:36 -07:00 |
|
tangxifan
|
0310dafe42
|
add accessors to LBRouter
|
2020-02-18 18:35:00 -07:00 |
|
tangxifan
|
1799db810d
|
compilation error fix
|
2020-02-18 17:04:36 -07:00 |
|
tangxifan
|
d58d14df8e
|
start encapsulate the whole lb router in an object
|
2020-02-18 16:50:56 -07:00 |
|
tangxifan
|
ed25ccc70f
|
start refactoring lb router in openfpga namespace
|
2020-02-18 12:00:27 -07:00 |
|
tangxifan
|
ef11482a95
|
fix dependency error in pack_types header file
|
2020-02-18 11:36:16 -07:00 |
|
tangxifan
|
6060440b97
|
fine tuning for the verbose output
|
2020-02-17 21:14:15 -07:00 |
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tangxifan
|
409b3f6896
|
add lb_rr_graph builder for the refactored version
|
2020-02-17 21:11:56 -07:00 |
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tangxifan
|
8e97443410
|
start working on repack
|
2020-02-17 17:57:43 -07:00 |
|
tangxifan
|
62e4f14e30
|
add lb_rr_graph to device annotation
|
2020-02-17 17:26:27 -07:00 |
|
tangxifan
|
6c69b52ded
|
Add missing file
|
2020-02-17 17:11:29 -07:00 |
|
tangxifan
|
92076c1460
|
refactored lb_rr_graph in the same principle of RRGraph object
|
2020-02-17 16:59:24 -07:00 |
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tangxifan
|
60f40a9657
|
use constant module manager as much as possible in Verilog writer
|
2020-02-16 16:35:26 -07:00 |
|
tangxifan
|
11775c370b
|
bring FPGA top module verilog writer online. Fabric Verilog generator done
|
2020-02-16 16:18:14 -07:00 |
|
tangxifan
|
e37ac8a098
|
add grid module Verilog writer
|
2020-02-16 16:04:41 -07:00 |
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tangxifan
|
c20caa1fa3
|
routing module Verilog writer is online
|
2020-02-16 14:47:54 -07:00 |
|
tangxifan
|
c6c3ef71f3
|
adapt all the Verilog submodule writers and bring it onlien
|
2020-02-16 13:35:18 -07:00 |
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tangxifan
|
99c3712b6f
|
adapt Verilog wire module writer
|
2020-02-16 12:59:37 -07:00 |
|
tangxifan
|
5cc68b0730
|
adapt LUT Verilog writer
|
2020-02-16 12:45:58 -07:00 |
|
tangxifan
|
105ccabecc
|
adapt memroy writer for verilog
|
2020-02-16 12:41:43 -07:00 |
|
tangxifan
|
c9d8120ae0
|
adapt Verilog mux writer
|
2020-02-16 12:35:41 -07:00 |
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tangxifan
|
a88c4bc954
|
add decode utils to libopenfpga and adapt local decoder writer in Verilog
|
2020-02-16 12:21:59 -07:00 |
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tangxifan
|
3efd1a2a6d
|
print verilog module writer online
|
2020-02-16 12:04:03 -07:00 |