71085247ac
[core] code format
2024-11-26 18:10:28 -08:00
296f318745
[core] fixed a big
2024-11-26 17:37:28 -08:00
29e15439d9
[lib] typo
2024-11-26 17:18:33 -08:00
10e3bf1165
[core] syntax
2024-11-26 16:52:30 -08:00
fdf8b9a57a
[lib] upgraded parser for new clock routing -related bitstream setting syntax
2024-11-26 14:54:52 -08:00
c5f0010feb
[lib] add missing files
2024-11-26 13:23:55 -08:00
8429c4b836
[lib] update parser
2024-11-26 13:23:34 -08:00
346aacefa9
[lib] add new feature clock tap routing to bitstream setting database
2024-11-26 12:43:27 -08:00
6e89943eb4
[core] code format
2024-11-25 16:22:01 -08:00
8577513995
[core] syntax
2024-11-25 15:37:39 -08:00
ed42c16f87
[core] support bitstream setting to overwrite default mode bits
2024-11-25 15:32:00 -08:00
94005fea99
[lib] update API for bitstream setting default mode overwrite
2024-11-25 11:20:47 -08:00
a10c683591
[lib] update parser to support bitstream setting default mode syntax
2024-11-25 11:10:07 -08:00
4533d160c5
[core] developming default mode overwrite through bitstream setting file
2024-11-24 22:20:59 -08:00
8e04d473f2
[core] code format
2024-09-18 21:10:31 -07:00
44a07704ff
[core] add check codes for last stage pgl model
2024-09-18 21:10:02 -07:00
f6b645fd25
[core] code format
2024-09-18 17:44:55 -07:00
82878063c1
[core] syntax
2024-09-18 17:32:04 -07:00
47e30c3e4b
[core] support last stage mux
2024-09-18 17:26:44 -07:00
0d9f1a3c6b
Forward searching the config bit + some minor refactor
2024-07-28 19:12:34 -07:00
9882394c8b
Use archfpga_throw
2024-07-28 02:53:18 -07:00
2a3d69aded
Update code based on feedback
2024-07-28 02:37:15 -07:00
933155b08f
Update test flow
2024-07-27 23:52:54 -07:00
e60777d23e
Use Bitstream Setting XML
2024-07-26 01:36:49 -07:00
3afb92d6a5
[core] code format
2024-06-30 22:48:15 -07:00
1fd974d544
[core] fixed a bug where clock network size cannot impact global port on top module
2024-06-29 17:35:47 -07:00
4640e74e7e
[core] code format
2024-06-25 12:25:16 -07:00
66af73e91e
[lib] now accept reset and set in programmable clock network
2024-06-25 12:24:46 -07:00
ca6e2f9831
[core] code format
2024-05-20 13:41:35 -07:00
b15e169490
[core] fixed a bug where wire model is expected on direct connections
2024-05-20 12:45:49 -07:00
9d87e99539
[lib] typo on keywords in XML parser
2024-05-20 11:15:43 -07:00
926b9e9739
[core] code format
2024-05-18 12:33:19 -07:00
3b93bea3d1
[core] syntax
2024-05-18 12:29:38 -07:00
be1d7517c9
[doc] rework out-of-date syntax
2024-05-17 19:25:35 -07:00
0d8c21ca84
[core] add new type 'part_of_cb' for tile direct connections
2024-05-17 18:59:53 -07:00
36d37289fe
[lib] add missing header required by clang-11+
2024-05-05 21:21:36 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
76f446caec
[core] fixed a bug
2023-09-25 21:13:11 -07:00
3adf81046a
[core] code format
2023-09-25 17:22:26 -07:00
5e269e8bc4
[core] support port merging at grid modules
2023-09-25 17:21:58 -07:00
fd99dafad7
[core] code format
2023-09-25 16:51:01 -07:00
96f36a96dd
[core] syntax
2023-09-25 16:50:30 -07:00
ca715f4c82
[core] developing parser to support subtile port merge
2023-09-25 16:46:34 -07:00
d3895c3dc0
[core] code format
2023-08-03 17:34:25 -07:00
23643f3fb1
[core] developing the physical memory block builder
2023-07-31 22:57:26 -07:00
e20ac5f272
[core] fixed a bug which cause configuration protocols other than ccff failed
2023-04-24 22:46:46 +08:00
18b078d1d5
[core] fixed bugs which cause ci failed
2023-04-24 21:20:07 +08:00
667d9df028
[core] developing testbench generator for ccff v2
2023-04-24 11:36:21 +08:00
ba90f5020b
[core] fixed some bugs which cause netlist generation failed
2023-04-23 16:48:14 +08:00
tangxifan
chungshien-chai
chungshien