riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[lib] update parser to support bitstream setting default mode syntax

This commit is contained in:
tangxifan 2024-11-25 11:10:07 -08:00
parent 4533d160c5
commit a10c683591
3 changed files with 64 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
libs/libarchopenfpga/src/bitstream_setting.h
View File

@ -109,9 +109,7 @@ class BitstreamSetting {
const BitstreamDefaultModeSettingId& default_mode_setting_id) const;
std::vector<std::string> default_mode_parent_mode_names(
const BitstreamDefaultModeSettingId& default_mode_setting_id) const;
vtr::Rect<size_t> default_mode_coord(
const BitstreamDefaultModeSettingId& default_mode_setting_id) const;
vtr::Point<size_t> default_mode_subtile(
std::string default_mode_bits(
const BitstreamDefaultModeSettingId& default_mode_setting_id) const;
std::string interconnect_name(
@ -142,8 +140,7 @@ class BitstreamSetting {
const std::string& pb_type_name,
const std::vector<std::string>& parent_pb_type_names,
const std::vector<std::string>& parent_mode_names,
const std::string& mode_bits, const vtr::Rect<size_t>& coord, const vtr::Point<size_t>& subtile_range);
const std::string& mode_bits);
BitstreamInterconnectSettingId add_bitstream_interconnect_setting(
const std::string& interconnect_name,
@ -194,8 +191,6 @@ class BitstreamSetting {
vtr::vector<BitstreamDefaultModeSettingId, std::vector<std::string>>
default_mode_parent_mode_names_;
vtr::vector<BitstreamDefaultModeSettingId, std::string> pb_type_default_mode_bits_;
vtr::vector<BitstreamDefaultModeSettingId, vtr::Rect<size_t>> pb_type_coords_;
vtr::vector<BitstreamDefaultModeSettingId, vtr::Point<size_t>> pb_type_subtile_ranges_;
/* Interconnect-related settings:
* - Name of interconnect under a given pb_type

30
libs/libarchopenfpga/src/read_xml_bitstream_setting.cpp
View File

@ -56,6 +56,26 @@ static void read_xml_bitstream_pb_type_setting(
bitstream_setting.set_bitstream_offset(bitstream_pb_type_id, offset);
}
/********************************************************************
* Parse XML description for a pb_type annotation under a <default_mode_bits> XML node
*******************************************************************/
static void read_xml_bitstream_default_mode_setting(
pugi::xml_node& xml_pb_type, const pugiutil::loc_data& loc_data,
openfpga::BitstreamSetting& bitstream_setting) {
const std::string& name_attr =
get_attribute(xml_pb_type, "name", loc_data).as_string();
/* Parse the attributes for operating pb_type */
openfpga::PbParser operating_pb_parser(name_attr);
const std::string& mode_bits_attr =
get_attribute(xml_pb_type, "mode_bits", loc_data).as_string();
/* Add to bitstream setting */
bitstream_setting.add_bitstream_default_mode_setting(
operating_pb_parser.leaf(), operating_pb_parser.parents(),
operating_pb_parser.modes(), mode_bits_attr);
}
/********************************************************************
* Parse XML description for a pb_type annotation under a <interconect> XML node
*******************************************************************/
@ -137,18 +157,24 @@ openfpga::BitstreamSetting read_xml_bitstream_setting(
* each child should be named after <pb_type>
*/
for (pugi::xml_node xml_child : Node.children()) {
/* Error out if the XML child has an invalid name! */
/* Error out if the XML child has an invalid name!
* TODO: Use std::map or something similar to apply checks!
*/
if ((xml_child.name() != std::string("pb_type")) &&
(xml_child.name() != std::string("default_mode_bits")) &&
(xml_child.name() != std::string("interconnect")) &&
(xml_child.name() != std::string("non_fabric")) &&
(xml_child.name() != std::string("overwrite_bitstream"))) {
bad_tag(xml_child, loc_data, Node,
{"pb_type | interconnect | non_fabric | overwrite_bitstream"});
{"pb_type | interconnect | default_mode_bits | non_fabric | overwrite_bitstream"});
}
if (xml_child.name() == std::string("pb_type")) {
read_xml_bitstream_pb_type_setting(xml_child, loc_data,
bitstream_setting);
} else if (xml_child.name() == std::string("default_mode_bits")) {
read_xml_bitstream_default_mode_setting(xml_child, loc_data,
bitstream_setting);
} else if (xml_child.name() == std::string("interconnect")) {
read_xml_bitstream_interconnect_setting(xml_child, loc_data,
bitstream_setting);

34
libs/libarchopenfpga/src/write_xml_bitstream_setting.cpp
View File

@ -118,6 +118,33 @@ static void write_xml_bitstream_pb_type_setting(
<< "\n";
}
/********************************************************************
* A writer to output a bitstream pb_type setting to XML format
*******************************************************************/
static void write_xml_bitstream_pb_type_setting(
std::fstream& fp, const char* fname,
const openfpga::BitstreamSetting& bitstream_setting,
const BitstreamDefaultModeSettingId& bitstream_default_mode_setting_id) {
/* Validate the file stream */
openfpga::check_file_stream(fname, fp);
fp << "\t"
<< "<default_mode_bits";
/* Generate the full hierarchy name of the pb_type */
write_xml_attribute(fp, "name",
generate_bitstream_setting_pb_type_hierarchy_name(
bitstream_setting, bitstream_default_mode_setting_id)
.c_str());
write_xml_attribute(
fp, "mode_bits",
bitstream_setting.default_mode_bits(bitstream_default_mode_setting_id)
.c_str());
fp << "/>"
<< "\n";
}
/********************************************************************
* A writer to output a bitstream interconnect setting to XML format
*******************************************************************/
@ -166,6 +193,13 @@ void write_xml_bitstream_setting(
bitstream_pb_type_setting_id);
}
/* Write default_mode -related settings */
for (const auto& bitstream_default_mode_setting_id :
bitstream_setting.default_mode_settings()) {
write_xml_bitstream_default_mode_setting(fp, fname, bitstream_setting,
bitstream_default_mode_setting_id);
}
/* Write interconnect -related settings */
for (const auto& bitstream_interc_setting_id :
bitstream_setting.interconnect_settings()) {