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[core] code format

This commit is contained in:
tangxifan 2024-11-26 18:10:28 -08:00
parent 637dd08bea
commit 71085247ac
13 changed files with 148 additions and 96 deletions
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15
libs/libarchopenfpga/src/bitstream_setting.cpp
View File

@ -30,7 +30,6 @@ BitstreamSetting::clock_routing_settings() const {
clock_routing_setting_ids_.end());
}
BitstreamSetting::bitstream_interconnect_setting_range
BitstreamSetting::interconnect_settings() const {
return vtr::make_range(interconnect_setting_ids_.begin(),
@ -135,15 +134,15 @@ std::string BitstreamSetting::default_mode_bits_to_string(
std::string BitstreamSetting::clock_routing_network(
const BitstreamClockRoutingSettingId& clock_routing_setting_id) const {
VTR_ASSERT(true ==
valid_bitstream_clock_routing_setting_id(clock_routing_setting_id));
VTR_ASSERT(
true == valid_bitstream_clock_routing_setting_id(clock_routing_setting_id));
return clock_routing_network_names_[clock_routing_setting_id];
}
BasicPort BitstreamSetting::clock_routing_pin(
const BitstreamClockRoutingSettingId& clock_routing_setting_id) const {
VTR_ASSERT(true ==
valid_bitstream_clock_routing_setting_id(clock_routing_setting_id));
VTR_ASSERT(
true == valid_bitstream_clock_routing_setting_id(clock_routing_setting_id));
return clock_routing_pins_[clock_routing_setting_id];
}
@ -245,8 +244,7 @@ BitstreamSetting::add_bitstream_default_mode_setting(
BitstreamClockRoutingSettingId
BitstreamSetting::add_bitstream_clock_routing_setting(
const std::string& ntwk_name,
const BasicPort& pin) {
const std::string& ntwk_name, const BasicPort& pin) {
BitstreamClockRoutingSettingId clock_routing_setting_id =
BitstreamClockRoutingSettingId(clock_routing_setting_ids_.size());
clock_routing_setting_ids_.push_back(clock_routing_setting_id);
@ -326,7 +324,8 @@ bool BitstreamSetting::valid_bitstream_default_mode_setting_id(
bool BitstreamSetting::valid_bitstream_clock_routing_setting_id(
const BitstreamClockRoutingSettingId& clock_routing_setting_id) const {
return (size_t(clock_routing_setting_id) < clock_routing_setting_ids_.size()) &&
return (size_t(clock_routing_setting_id) <
clock_routing_setting_ids_.size()) &&
(clock_routing_setting_id ==
clock_routing_setting_ids_[clock_routing_setting_id]);
}

8
libs/libarchopenfpga/src/bitstream_setting.h
View File

@ -9,9 +9,9 @@
#include <vector>
#include "bitstream_setting_fwd.h"
#include "openfpga_port.h"
#include "vtr_geometry.h"
#include "vtr_vector.h"
#include "openfpga_port.h"
/* namespace openfpga begins */
namespace openfpga {
@ -167,8 +167,7 @@ class BitstreamSetting {
/* Clock routing settings */
BitstreamClockRoutingSettingId add_bitstream_clock_routing_setting(
const std::string& ntwk_name,
const BasicPort& pin);
const std::string& ntwk_name, const BasicPort& pin);
/* Interconnect settings */
BitstreamInterconnectSettingId add_bitstream_interconnect_setting(
@ -234,8 +233,7 @@ class BitstreamSetting {
clock_routing_setting_ids_;
vtr::vector<BitstreamClockRoutingSettingId, std::string>
clock_routing_network_names_;
vtr::vector<BitstreamClockRoutingSettingId, BasicPort>
clock_routing_pins_;
vtr::vector<BitstreamClockRoutingSettingId, BasicPort> clock_routing_pins_;
/* Interconnect-related settings:
* - Name of interconnect under a given pb_type

14
libs/libarchopenfpga/src/bitstream_setting_xml_constants.h
View File

@ -3,14 +3,17 @@
/* Constants required by XML parser */
constexpr const char* XML_BITSTREAM_SETTING_ROOT_NAME = "openfpga_bitstream_setting";
constexpr const char* XML_BITSTREAM_SETTING_ROOT_NAME =
"openfpga_bitstream_setting";
/* Pb-type XML syntax */
constexpr const char* XML_PB_TYPE_NODE_NAME = "pb_type";
constexpr const char* XML_PB_TYPE_ATTRIBUTE_NAME = "name";
constexpr const char* XML_PB_TYPE_ATTRIBUTE_SOURCE = "source";
constexpr const char* XML_PB_TYPE_ATTRIBUTE_CONTENT = "content";
constexpr const char* XML_PB_TYPE_ATTRIBUTE_IS_MODE_SELECT_BITSTREAM = "is_mode_select_bitstream";
constexpr const char* XML_PB_TYPE_ATTRIBUTE_BITSTREAM_OFFSET = "bitstream_offset";
constexpr const char* XML_PB_TYPE_ATTRIBUTE_IS_MODE_SELECT_BITSTREAM =
"is_mode_select_bitstream";
constexpr const char* XML_PB_TYPE_ATTRIBUTE_BITSTREAM_OFFSET =
"bitstream_offset";
/* Default mode bits XML syntax */
constexpr const char* XML_DEFAULT_MODE_BITS_NODE_NAME = "default_mode_bits";
@ -42,6 +45,9 @@ constexpr const char* XML_OVERWRITE_BITSTREAM_ATTRIBUTE_PATH = "path";
constexpr const char* XML_OVERWRITE_BITSTREAM_ATTRIBUTE_VALUE = "value";
/* Sanity check constants */
constexpr const char* XML_VALID_NODE_NAMES[] = {XML_BITSTREAM_SETTING_ROOT_NAME, XML_DEFAULT_MODE_BITS_NODE_NAME, XML_INTERCONNECT_NODE_NAME, XML_CLOCK_ROUTING_NODE_NAME, XML_NON_FABRIC_NODE_NAME, XML_OVERWRITE_BITSTREAM_NODE_NAME};
constexpr const char* XML_VALID_NODE_NAMES[] = {
XML_BITSTREAM_SETTING_ROOT_NAME, XML_DEFAULT_MODE_BITS_NODE_NAME,
XML_INTERCONNECT_NODE_NAME, XML_CLOCK_ROUTING_NODE_NAME,
XML_NON_FABRIC_NODE_NAME, XML_OVERWRITE_BITSTREAM_NODE_NAME};
#endif

89
libs/libarchopenfpga/src/read_xml_bitstream_setting.cpp
View File

@ -18,10 +18,10 @@
/* Headers from libarchfpga */
#include "arch_error.h"
#include "bitstream_setting_xml_constants.h"
#include "read_xml_bitstream_setting.h"
#include "read_xml_openfpga_arch_utils.h"
#include "read_xml_util.h"
#include "bitstream_setting_xml_constants.h"
/********************************************************************
* Parse XML description for a pb_type annotation under a <pb_type> XML node
@ -30,11 +30,14 @@ static void read_xml_bitstream_pb_type_setting(
pugi::xml_node& xml_pb_type, const pugiutil::loc_data& loc_data,
openfpga::BitstreamSetting& bitstream_setting) {
const std::string& name_attr =
get_attribute(xml_pb_type, XML_PB_TYPE_ATTRIBUTE_NAME, loc_data).as_string();
get_attribute(xml_pb_type, XML_PB_TYPE_ATTRIBUTE_NAME, loc_data)
.as_string();
const std::string& source_attr =
get_attribute(xml_pb_type, XML_PB_TYPE_ATTRIBUTE_SOURCE, loc_data).as_string();
get_attribute(xml_pb_type, XML_PB_TYPE_ATTRIBUTE_SOURCE, loc_data)
.as_string();
const std::string& content_attr =
get_attribute(xml_pb_type, XML_PB_TYPE_ATTRIBUTE_CONTENT, loc_data).as_string();
get_attribute(xml_pb_type, XML_PB_TYPE_ATTRIBUTE_CONTENT, loc_data)
.as_string();
/* Parse the attributes for operating pb_type */
openfpga::PbParser operating_pb_parser(name_attr);
@ -47,15 +50,16 @@ static void read_xml_bitstream_pb_type_setting(
/* Parse if the bitstream overwritting is applied to mode bits of a pb_type */
const bool& is_mode_select_bitstream =
get_attribute(xml_pb_type, XML_PB_TYPE_ATTRIBUTE_IS_MODE_SELECT_BITSTREAM, loc_data,
pugiutil::ReqOpt::OPTIONAL)
get_attribute(xml_pb_type, XML_PB_TYPE_ATTRIBUTE_IS_MODE_SELECT_BITSTREAM,
loc_data, pugiutil::ReqOpt::OPTIONAL)
.as_bool(false);
bitstream_setting.set_mode_select_bitstream(bitstream_pb_type_id,
is_mode_select_bitstream);
const int& offset = get_attribute(xml_pb_type, XML_PB_TYPE_ATTRIBUTE_BITSTREAM_OFFSET, loc_data,
pugiutil::ReqOpt::OPTIONAL)
.as_int(0);
const int& offset =
get_attribute(xml_pb_type, XML_PB_TYPE_ATTRIBUTE_BITSTREAM_OFFSET, loc_data,
pugiutil::ReqOpt::OPTIONAL)
.as_int(0);
bitstream_setting.set_bitstream_offset(bitstream_pb_type_id, offset);
}
@ -67,12 +71,15 @@ static void read_xml_bitstream_default_mode_setting(
pugi::xml_node& xml_pb_type, const pugiutil::loc_data& loc_data,
openfpga::BitstreamSetting& bitstream_setting) {
const std::string& name_attr =
get_attribute(xml_pb_type, XML_DEFAULT_MODE_BITS_ATTRIBUTE_NAME, loc_data).as_string();
get_attribute(xml_pb_type, XML_DEFAULT_MODE_BITS_ATTRIBUTE_NAME, loc_data)
.as_string();
/* Parse the attributes for operating pb_type */
openfpga::PbParser operating_pb_parser(name_attr);
const std::string& mode_bits_attr =
get_attribute(xml_pb_type, XML_DEFAULT_MODE_BITS_ATTRIBUTE_MODE_BITS, loc_data).as_string();
get_attribute(xml_pb_type, XML_DEFAULT_MODE_BITS_ATTRIBUTE_MODE_BITS,
loc_data)
.as_string();
std::vector<size_t> mode_bits =
parse_mode_bits(xml_pb_type, loc_data, mode_bits_attr);
@ -90,21 +97,28 @@ static void read_xml_bitstream_clock_routing_setting(
pugi::xml_node& xml_clk_routing, const pugiutil::loc_data& loc_data,
openfpga::BitstreamSetting& bitstream_setting) {
const std::string& ntwk_attr =
get_attribute(xml_clk_routing, XML_CLOCK_ROUTING_ATTRIBUTE_NETWORK, loc_data).as_string();
get_attribute(xml_clk_routing, XML_CLOCK_ROUTING_ATTRIBUTE_NETWORK,
loc_data)
.as_string();
const std::string& pin_attr =
get_attribute(xml_clk_routing, XML_CLOCK_ROUTING_ATTRIBUTE_PIN, loc_data).as_string();
get_attribute(xml_clk_routing, XML_CLOCK_ROUTING_ATTRIBUTE_PIN, loc_data)
.as_string();
/* Parse the port and apply sanity checks */
openfpga::PortParser port_parser(pin_attr);
openfpga::BasicPort pin = port_parser.port();
if (!pin.is_valid()) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_clk_routing),
"Invalid pin '%s' which should be valid port. For example, clk[1:1]\n", pin_attr.c_str());
archfpga_throw(
loc_data.filename_c_str(), loc_data.line(xml_clk_routing),
"Invalid pin '%s' which should be valid port. For example, clk[1:1]\n",
pin_attr.c_str());
}
if (1 != pin.get_width()) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_clk_routing),
"Invalid pin '%s' with a width of '%lu'. Only allow pin definition with width of 1. For example, clk[2:2]\n", pin_attr.c_str(), pin.get_width());
}
"Invalid pin '%s' with a width of '%lu'. Only allow pin "
"definition with width of 1. For example, clk[2:2]\n",
pin_attr.c_str(), pin.get_width());
}
/* Add to bitstream setting */
bitstream_setting.add_bitstream_clock_routing_setting(ntwk_attr, pin);
@ -117,9 +131,12 @@ static void read_xml_bitstream_interconnect_setting(
pugi::xml_node& xml_pb_type, const pugiutil::loc_data& loc_data,
openfpga::BitstreamSetting& bitstream_setting) {
const std::string& name_attr =
get_attribute(xml_pb_type, XML_INTERCONNECT_ATTRIBUTE_NAME, loc_data).as_string();
get_attribute(xml_pb_type, XML_INTERCONNECT_ATTRIBUTE_NAME, loc_data)
.as_string();
const std::string& default_path_attr =
get_attribute(xml_pb_type, XML_INTERCONNECT_ATTRIBUTE_DEFAULT_PATH, loc_data).as_string();
get_attribute(xml_pb_type, XML_INTERCONNECT_ATTRIBUTE_DEFAULT_PATH,
loc_data)
.as_string();
/* Parse the attributes for operating pb_type */
openfpga::PbParser operating_pb_parser(name_attr);
@ -138,19 +155,24 @@ static void read_xml_non_fabric_bitstream_setting(
pugi::xml_node& xml_non_fabric, const pugiutil::loc_data& loc_data,
openfpga::BitstreamSetting& bitstream_setting) {
const std::string& name_attr =
get_attribute(xml_non_fabric, XML_NON_FABRIC_ATTRIBUTE_NAME, loc_data).as_string();
get_attribute(xml_non_fabric, XML_NON_FABRIC_ATTRIBUTE_NAME, loc_data)
.as_string();
const std::string& file_attr =
get_attribute(xml_non_fabric, XML_NON_FABRIC_ATTRIBUTE_FILE, loc_data).as_string();
get_attribute(xml_non_fabric, XML_NON_FABRIC_ATTRIBUTE_FILE, loc_data)
.as_string();
/* Add to non-fabric */
bitstream_setting.add_non_fabric(name_attr, file_attr);
for (pugi::xml_node xml_child : xml_non_fabric.children()) {
if (xml_child.name() != std::string(XML_NON_FABRIC_PB_NODE_NAME)) {
bad_tag(xml_child, loc_data, xml_non_fabric, {XML_NON_FABRIC_PB_NODE_NAME});
bad_tag(xml_child, loc_data, xml_non_fabric,
{XML_NON_FABRIC_PB_NODE_NAME});
}
const std::string& pb_name_attr =
get_attribute(xml_child, XML_NON_FABRIC_PB_ATTRIBUTE_NAME, loc_data).as_string();
get_attribute(xml_child, XML_NON_FABRIC_PB_ATTRIBUTE_NAME, loc_data)
.as_string();
const std::string& content_attr =
get_attribute(xml_child, XML_NON_FABRIC_PB_ATTRIBUTE_CONTENT, loc_data).as_string();
get_attribute(xml_child, XML_NON_FABRIC_PB_ATTRIBUTE_CONTENT, loc_data)
.as_string();
/* Add PB to non-fabric */
bitstream_setting.add_non_fabric_pb(pb_name_attr, content_attr);
}
@ -165,12 +187,15 @@ static void read_xml_overwrite_bitstream_setting(
// Loopthrough bit
for (pugi::xml_node xml_bit : xml_overwrite_bitstream.children()) {
if (xml_bit.name() != std::string(XML_OVERWRITE_BITSTREAM_ATTRIBUTE_BIT)) {
bad_tag(xml_bit, loc_data, xml_overwrite_bitstream, {XML_OVERWRITE_BITSTREAM_ATTRIBUTE_BIT});
bad_tag(xml_bit, loc_data, xml_overwrite_bitstream,
{XML_OVERWRITE_BITSTREAM_ATTRIBUTE_BIT});
}
const std::string& path_attr =
get_attribute(xml_bit, XML_OVERWRITE_BITSTREAM_ATTRIBUTE_PATH, loc_data).as_string();
get_attribute(xml_bit, XML_OVERWRITE_BITSTREAM_ATTRIBUTE_PATH, loc_data)
.as_string();
const std::string& value_attr =
get_attribute(xml_bit, XML_OVERWRITE_BITSTREAM_ATTRIBUTE_VALUE, loc_data).as_string();
get_attribute(xml_bit, XML_OVERWRITE_BITSTREAM_ATTRIBUTE_VALUE, loc_data)
.as_string();
if (value_attr != "0" && value_attr != "1") {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_bit),
"Invalid value of overwrite_bitstream bit. Expect [0|1]");
@ -191,7 +216,7 @@ openfpga::BitstreamSetting read_xml_bitstream_setting(
* each child should be named after <pb_type>
*/
for (pugi::xml_node xml_child : Node.children()) {
bool valid_node = false;
bool valid_node = false;
for (auto valid_node_name : XML_VALID_NODE_NAMES) {
if (xml_child.name() == std::string(valid_node_name)) {
valid_node = true;
@ -209,12 +234,13 @@ openfpga::BitstreamSetting read_xml_bitstream_setting(
if (xml_child.name() == std::string(XML_PB_TYPE_NODE_NAME)) {
read_xml_bitstream_pb_type_setting(xml_child, loc_data,
bitstream_setting);
} else if (xml_child.name() == std::string(XML_DEFAULT_MODE_BITS_NODE_NAME)) {
} else if (xml_child.name() ==
std::string(XML_DEFAULT_MODE_BITS_NODE_NAME)) {
read_xml_bitstream_default_mode_setting(xml_child, loc_data,
bitstream_setting);
} else if (xml_child.name() == std::string(XML_CLOCK_ROUTING_NODE_NAME)) {
read_xml_bitstream_clock_routing_setting(xml_child, loc_data,
bitstream_setting);
bitstream_setting);
} else if (xml_child.name() == std::string(XML_INTERCONNECT_NODE_NAME)) {
read_xml_bitstream_interconnect_setting(xml_child, loc_data,
bitstream_setting);
@ -222,7 +248,8 @@ openfpga::BitstreamSetting read_xml_bitstream_setting(
read_xml_non_fabric_bitstream_setting(xml_child, loc_data,
bitstream_setting);
} else {
VTR_ASSERT_SAFE(xml_child.name() == std::string(XML_OVERWRITE_BITSTREAM_NODE_NAME));
VTR_ASSERT_SAFE(xml_child.name() ==
std::string(XML_OVERWRITE_BITSTREAM_NODE_NAME));
read_xml_overwrite_bitstream_setting(xml_child, loc_data,
bitstream_setting);
}

17
libs/libarchopenfpga/src/write_xml_bitstream_setting.cpp
View File

@ -11,9 +11,9 @@
#include "vtr_log.h"
/* Headers from readarchopenfpga library */
#include "bitstream_setting_xml_constants.h"
#include "write_xml_bitstream_setting.h"
#include "write_xml_utils.h"
#include "bitstream_setting_xml_constants.h"
/********************************************************************
* Generate the full hierarchy name for a pb_type in bitstream setting
@ -198,14 +198,15 @@ static void write_xml_bitstream_clock_routing_setting(
<< "<" << XML_CLOCK_ROUTING_NODE_NAME;
/* Generate the full hierarchy name of the pb_type */
write_xml_attribute(fp, XML_CLOCK_ROUTING_ATTRIBUTE_NETWORK,
bitstream_setting.clock_routing_network(bitstream_clock_routing_setting_id)
.c_str());
write_xml_attribute(
fp, XML_CLOCK_ROUTING_ATTRIBUTE_NETWORK,
bitstream_setting.clock_routing_network(bitstream_clock_routing_setting_id)
.c_str());
write_xml_attribute(
fp, XML_CLOCK_ROUTING_ATTRIBUTE_PIN,
bitstream_setting
.clock_routing_pin(bitstream_clock_routing_setting_id).to_verilog_string()
bitstream_setting.clock_routing_pin(bitstream_clock_routing_setting_id)
.to_verilog_string()
.c_str());
fp << "/>"
<< "\n";
@ -269,8 +270,8 @@ void write_xml_bitstream_setting(
/* Write clock_routing -related settings */
for (const auto& bitstream_clock_routing_setting_id :
bitstream_setting.clock_routing_settings()) {
write_xml_bitstream_clock_routing_setting(fp, fname, bitstream_setting,
bitstream_clock_routing_setting_id);
write_xml_bitstream_clock_routing_setting(
fp, fname, bitstream_setting, bitstream_clock_routing_setting_id);
}
/* Write interconnect -related settings */

2
libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp
View File

@ -6,7 +6,7 @@
# Input file: /home/xifan/github/OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks.xsd
# md5sum of input file: 1db9d740309076fa51f61413bae1e072
@0x9cb54e2c8c367c87;
@0xc5bb4dab7879b418;
using Cxx = import "/capnp/c++.capnp";
$Cxx.namespace("ucap");

51
openfpga/src/annotation/annotate_bitstream_setting.cpp
View File

@ -212,26 +212,33 @@ static int annotate_bitstream_default_mode_setting(
}
/********************************************************************
* Annotate bitstream setting based on programmable clock network
* - Find the clock tree which is defined in the bitstream setting. Apply sanity check if it does not work
* - Mark id of the pin of clock tree to be routed and check if the one defined in bitstream setting is valid
* Annotate bitstream setting based on programmable clock network
* - Find the clock tree which is defined in the bitstream setting. Apply
*sanity check if it does not work
* - Mark id of the pin of clock tree to be routed and check if the one defined
*in bitstream setting is valid
*******************************************************************/
static int annotate_bitstream_clock_routing_setting(
const BitstreamSetting& bitstream_setting,
const ClockNetwork& clk_ntwk,
const BitstreamSetting& bitstream_setting, const ClockNetwork& clk_ntwk,
VprBitstreamAnnotation& vpr_bitstream_annotation) {
/* For an empty clock network, throw warning that nothing will be done */
if (clk_ntwk.empty() && !bitstream_setting.clock_routing_settings().empty()) {
VTR_LOG_WARN("Clock network is empty. No bitstream settings related to clock routing will be applied!\n");
VTR_LOG_WARN(
"Clock network is empty. No bitstream settings related to clock routing "
"will be applied!\n");
return CMD_EXEC_SUCCESS;
}
for (const auto& bitstream_clock_routing_setting_id :
bitstream_setting.clock_routing_settings()) {
/* Validate if the given clock network name is valid */
std::string ntwk_name = bitstream_setting.clock_routing_network(bitstream_clock_routing_setting_id);
std::string ntwk_name = bitstream_setting.clock_routing_network(
bitstream_clock_routing_setting_id);
ClockTreeId tree_id = clk_ntwk.find_tree(ntwk_name);
if (!clk_ntwk.valid_tree_id(tree_id)) {
VTR_LOG_ERROR("Invalid clock network name '%s' from bitstream setting, which is not defined in the clock network description!\n", ntwk_name.c_str());
VTR_LOG_ERROR(
"Invalid clock network name '%s' from bitstream setting, which is not "
"defined in the clock network description!\n",
ntwk_name.c_str());
/* Show valid clock network names */
VTR_LOG("Valid clock network names are as follows\n");
for (auto curr_tree_id : clk_ntwk.trees()) {
@ -241,21 +248,36 @@ static int annotate_bitstream_clock_routing_setting(
}
/* Valid the port */
BasicPort tree_port = clk_ntwk.tree_global_port(tree_id);
BasicPort wanted_pin = bitstream_setting.clock_routing_pin(bitstream_clock_routing_setting_id);
BasicPort wanted_pin =
bitstream_setting.clock_routing_pin(bitstream_clock_routing_setting_id);
if (wanted_pin.get_width() != 1) {
VTR_LOG_ERROR("Invalid clock pin definition '%s' from bitstream setting for clock network name '%s', whose port width must be 1!\n", wanted_pin.to_verilog_string().c_str(), ntwk_name.c_str());
VTR_LOG_ERROR(
"Invalid clock pin definition '%s' from bitstream setting for clock "
"network name '%s', whose port width must be 1!\n",
wanted_pin.to_verilog_string().c_str(), ntwk_name.c_str());
return CMD_EXEC_FATAL_ERROR;
}
if (!tree_port.mergeable(wanted_pin)) {
VTR_LOG_ERROR("Invalid clock pin definition '%s' from bitstream setting for clock network name '%s', which does not match the name of pin '%s' in the clock network description!\n", wanted_pin.to_verilog_string().c_str(), ntwk_name.c_str(), tree_port.to_verilog_string().c_str());
VTR_LOG_ERROR(
"Invalid clock pin definition '%s' from bitstream setting for clock "
"network name '%s', which does not match the name of pin '%s' in the "
"clock network description!\n",
wanted_pin.to_verilog_string().c_str(), ntwk_name.c_str(),
tree_port.to_verilog_string().c_str());
return CMD_EXEC_FATAL_ERROR;
}
if (!tree_port.contained(wanted_pin)) {
VTR_LOG_ERROR("Invalid clock pin definition '%s' from bitstream setting for clock network name '%s', which is out of the pin '%s' in the clock network description!\n", wanted_pin.to_verilog_string().c_str(), ntwk_name.c_str(), tree_port.to_verilog_string().c_str());
VTR_LOG_ERROR(
"Invalid clock pin definition '%s' from bitstream setting for clock "
"network name '%s', which is out of the pin '%s' in the clock network "
"description!\n",
wanted_pin.to_verilog_string().c_str(), ntwk_name.c_str(),
tree_port.to_verilog_string().c_str());
return CMD_EXEC_FATAL_ERROR;
}
/* All sanity check passed. Record the bitstream requirements */
ClockTreePinId tree_pin_id = clk_ntwk.pins(tree_id)[tree_port.find_ipin(wanted_pin)];
ClockTreePinId tree_pin_id =
clk_ntwk.pins(tree_id)[tree_port.find_ipin(wanted_pin)];
vpr_bitstream_annotation.set_clock_tap_routing_pin(tree_id, tree_pin_id);
}
return CMD_EXEC_SUCCESS;
@ -391,8 +413,7 @@ static int annotate_bitstream_interconnect_setting(
*******************************************************************/
int annotate_bitstream_setting(
const BitstreamSetting& bitstream_setting,
const DeviceContext& vpr_device_ctx,
const ClockNetwork& clk_ntwk,
const DeviceContext& vpr_device_ctx, const ClockNetwork& clk_ntwk,
VprDeviceAnnotation& vpr_device_annotation,
VprBitstreamAnnotation& vpr_bitstream_annotation) {
int status = CMD_EXEC_SUCCESS;

5
openfpga/src/annotation/annotate_bitstream_setting.h
View File

@ -4,9 +4,9 @@
/********************************************************************
* Include header files that are required by function declaration
*******************************************************************/
#include "clock_network.h"
#include "openfpga_context.h"
#include "vpr_context.h"
#include "clock_network.h"
/********************************************************************
* Function declaration
@ -17,8 +17,7 @@ namespace openfpga {
int annotate_bitstream_setting(
const BitstreamSetting& bitstream_setting,
const DeviceContext& vpr_device_ctx,
const ClockNetwork& clk_ntwk,
const DeviceContext& vpr_device_ctx, const ClockNetwork& clk_ntwk,
VprDeviceAnnotation& vpr_device_annotation,
VprBitstreamAnnotation& vpr_bitstream_annotation);

18
openfpga/src/annotation/route_clock_rr_graph.cpp
View File

@ -224,8 +224,7 @@ static int route_spine_taps(
const std::map<ClockTreePinId, ClusterNetId>& tree2clk_pin_map,
const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree,
const ClockSpineId& ispine, const ClockTreePinId& ipin,
const bool& force_tap_routing,
const bool& verbose) {
const bool& force_tap_routing, const bool& verbose) {
size_t spine_tap_cnt = 0;
/* Route the spine-to-IPIN connections (only for the last level) */
if (clk_ntwk.is_last_level(ispine)) {
@ -423,8 +422,7 @@ static int rec_expand_and_route_clock_spine(
const std::map<ClockTreePinId, ClusterNetId>& tree2clk_pin_map,
const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree,
const ClockSpineId& curr_spine, const ClockTreePinId& curr_pin,
const bool& disable_unused_spines,
const bool& force_tap_routing,
const bool& disable_unused_spines, const bool& force_tap_routing,
const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
bool curr_spine_usage = false;
@ -432,7 +430,8 @@ static int rec_expand_and_route_clock_spine(
/* For last level, we just connect tap points */
status = route_spine_taps(vpr_routing_annotation, curr_tap_usage, rr_graph,
clk_rr_lookup, rr_node_gnets, tree2clk_pin_map,
clk_ntwk, clk_tree, curr_spine, curr_pin, force_tap_routing, verbose);
clk_ntwk, clk_tree, curr_spine, curr_pin,
force_tap_routing, verbose);
if (CMD_EXEC_SUCCESS != status) {
return CMD_EXEC_FATAL_ERROR;
}
@ -607,7 +606,8 @@ static int route_clock_tree_rr_graph(
clk_ntwk.tree_name(clk_tree).c_str(), size_t(ipin));
continue;
}
/* Mark if tap point should be all routed regardless of usage (net mapping) */
/* Mark if tap point should be all routed regardless of usage (net mapping)
*/
bool force_tap_routing = false;
if (ipin == vpr_bitstream_annotation.clock_tap_routing_pin(clk_tree)) {
force_tap_routing = true;
@ -699,9 +699,9 @@ int route_clock_rr_graph(
VTR_LOGV(verbose, "Routing clock tree '%s'...\n",
clk_ntwk.tree_name(itree).c_str());
status = route_clock_tree_rr_graph(
vpr_routing_annotation, vpr_device_ctx.rr_graph, vpr_bitstream_annotation, clk_rr_lookup,
rr_node_gnets, tree2clk_pin_map, clk_ntwk, itree, disable_unused_trees,
disable_unused_spines, verbose);
vpr_routing_annotation, vpr_device_ctx.rr_graph, vpr_bitstream_annotation,
clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, itree,
disable_unused_trees, disable_unused_spines, verbose);
if (status == CMD_EXEC_FATAL_ERROR) {
return status;
}

2
openfpga/src/annotation/route_clock_rr_graph.h
View File

@ -7,10 +7,10 @@
#include "clock_network.h"
#include "pin_constraints.h"
#include "rr_clock_spatial_lookup.h"
#include "vpr_bitstream_annotation.h"
#include "vpr_clustering_annotation.h"
#include "vpr_context.h"
#include "vpr_routing_annotation.h"
#include "vpr_bitstream_annotation.h"
/********************************************************************
* Function declaration

7
openfpga/src/annotation/vpr_bitstream_annotation.cpp
View File

@ -118,7 +118,6 @@ ClockTreePinId VprBitstreamAnnotation::clock_tap_routing_pin(
return ClockTreePinId::INVALID();
}
/************************************************************************
* Public mutators
***********************************************************************/
@ -166,8 +165,10 @@ void VprBitstreamAnnotation::set_clock_tap_routing_pin(
const ClockTreeId& tree_id, const ClockTreePinId& tree_pin_id) {
auto result = clock_tap_routing_pins_.find(tree_id);
if (result != clock_tap_routing_pins_.end()) {
VTR_LOG_WARN("Overwrite the clock tree pin '%lu' for clock tree '%d' tap routing (Was pin '%lu')\n",
size_t(tree_pin_id), size_t(tree_id), size_t(result->second));
VTR_LOG_WARN(
"Overwrite the clock tree pin '%lu' for clock tree '%d' tap routing (Was "
"pin '%lu')\n",
size_t(tree_pin_id), size_t(tree_id), size_t(result->second));
}
clock_tap_routing_pins_[tree_id] = tree_pin_id;
}

9
openfpga/src/annotation/vpr_bitstream_annotation.h
View File

@ -8,8 +8,8 @@
#include <string>
/* Header from vpr library */
#include "vpr_context.h"
#include "clock_network.h"
#include "vpr_context.h"
/* Begin namespace openfpga */
namespace openfpga {
@ -64,7 +64,8 @@ class VprBitstreamAnnotation {
const size_t& offset);
void set_interconnect_default_path_id(t_interconnect* interconnect,
const size_t& default_path_id);
void set_clock_tap_routing_pin(const ClockTreeId& tree_id, const ClockTreePinId& tree_pin_id);
void set_clock_tap_routing_pin(const ClockTreeId& tree_id,
const ClockTreePinId& tree_pin_id);
private: /* Internal data */
/* For regular bitstreams */
@ -91,8 +92,8 @@ class VprBitstreamAnnotation {
*/
std::map<t_interconnect*, size_t> interconnect_default_path_ids_;
/* Mark the clock tree pin for which all the tap points of clock tree should be routed through
* Note that for each clock tree, only one pin is allowed
/* Mark the clock tree pin for which all the tap points of clock tree should
* be routed through Note that for each clock tree, only one pin is allowed
*/
std::map<ClockTreeId, ClockTreePinId> clock_tap_routing_pins_;
};

7
openfpga/src/base/openfpga_link_arch_template.h
View File

@ -177,8 +177,7 @@ int link_arch_template(T& openfpga_ctx, const Command& cmd,
if (CMD_EXEC_FATAL_ERROR ==
annotate_bitstream_setting(
openfpga_ctx.bitstream_setting(), g_vpr_ctx.device(),
openfpga_ctx.clock_arch(),
openfpga_ctx.mutable_vpr_device_annotation(),
openfpga_ctx.clock_arch(), openfpga_ctx.mutable_vpr_device_annotation(),
openfpga_ctx.mutable_vpr_bitstream_annotation())) {
return CMD_EXEC_FATAL_ERROR;
}
@ -234,8 +233,8 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd,
openfpga_ctx.mutable_vpr_routing_annotation(),
openfpga_ctx.vpr_clustering_annotation(), g_vpr_ctx.device(),
g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.placement(),
openfpga_ctx.vpr_bitstream_annotation(),
openfpga_ctx.clock_rr_lookup(), openfpga_ctx.clock_arch(), pin_constraints,
openfpga_ctx.vpr_bitstream_annotation(), openfpga_ctx.clock_rr_lookup(),
openfpga_ctx.clock_arch(), pin_constraints,
cmd_context.option_enable(cmd, opt_disable_unused_trees),
cmd_context.option_enable(cmd, opt_disable_unused_spines),
cmd_context.option_enable(cmd, opt_verbose));