6daee8c2c8
bug fixed in the example architecture
2020-04-07 16:03:34 -06:00
628ea3b654
improve adder chain arch XML to support sequential output for sumout
2020-04-07 15:39:37 -06:00
26d1261c1f
add test cases using shift registers
2020-04-07 15:09:10 -06:00
e61e7167b3
update circuit model names in the example tree-like MUX architecture
2020-04-07 11:27:16 -06:00
0eeb8e5317
clean up example architecture XML by removing redundant syntax
2020-04-07 11:24:42 -06:00
6d6295ef93
Add test cases about using standard cell mux2
2020-04-07 11:12:47 -06:00
d39d7a68ce
add test cases for using tree-like multiplexer
2020-04-07 10:46:49 -06:00
92a3a444f9
update VPR7 to support global I/O ports
2020-04-06 20:44:00 -06:00
13cd48c119
add support on packable/unpackable modes in VPR architecture
2020-04-06 16:07:49 -06:00
6eb125ec2a
Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML
2020-04-06 14:09:52 -06:00
3369d724e9
bug fixing in Verilog top-level testbench generation
2020-04-05 17:50:11 -06:00
decc1dc4b2
debugged global gp input/output port support
2020-04-05 17:39:30 -06:00
bcb86801fa
bug fixed in gpio naming for module manager ports
2020-04-05 17:26:44 -06:00
5f4e7dc5d4
support gpinput and gpoutput ports in module manager and circuit library
2020-04-05 16:52:21 -06:00
bc47b3ca94
update verilog module writer to the global spy ports
2020-04-05 16:04:13 -06:00
8b583b7917
debugging spy port builder in module manager
2020-04-05 16:01:25 -06:00
ca45efd13d
add testing script for the spy io
2020-04-05 15:24:40 -06:00
3b63ad6657
add test openfpga arch XML with spy pad
2020-04-05 15:23:07 -06:00
836f722f20
start supporting global output ports in module manager
2020-04-05 15:19:46 -06:00
32c74ad811
added FPGA architecture with I/Os on the left and right sides
2020-04-01 15:46:38 -06:00
63306ce3a0
add comments to explain the memory organization in the top-level module
2020-04-01 11:05:30 -06:00
07e1979498
add architecture examples on wide memory blocks (width=2). tileable routing is working
2020-03-28 15:41:26 -06:00
ff9cc50527
relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
2020-03-27 20:09:50 -06:00
e601a648cc
relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
2020-03-27 19:07:34 -06:00
34a1b61ecb
add an example FPGA architecture with AIB interface at the right side of I/Os
2020-03-27 18:45:27 -06:00
4bf0a63ae6
bug fixed for multiple io types defined in FPGA architectures
2020-03-27 16:32:15 -06:00
7c9c2451f2
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
2020-03-27 16:03:42 -06:00
b09b051249
add all the test cases considering tileable, carry chain, direct connection and memory blocks
2020-03-27 13:58:35 -06:00
e47a0a4422
add through channel architecture example
2020-03-27 11:32:44 -06:00
91a618466d
bug fixing for rr_graph.clear() function
2020-03-27 10:52:48 -06:00
329b0a9cf1
add options to enable SDC constraints on zero-delay paths
2020-03-25 15:55:30 -06:00
4a0128f240
minor fix on the SDC format
2020-03-25 14:46:31 -06:00
c2e5d6b8e2
add options to dsiable SDC for non-clock global ports
2020-03-25 14:38:13 -06:00
787dc8ce83
added ASCII OpenFPGA logo in shell interface
2020-03-25 11:16:04 -06:00
b6bdf78d95
bug fixed for heterogeneous block instances in top module
2020-03-24 17:39:26 -06:00
610c71671f
experimentally developing through channels inside multi-width and multi-height grids.
...
Still debugging.
2020-03-24 16:47:45 -06:00
8a996ceae5
bug fixed in tileable routing when heterogeneous blocks are considered;
...
VPR have special rules in checking the coordinates of SOURCE and SINK nodes,
which is very different from the OPIN and IPIN nodes
Show respect to it here.
2020-03-24 13:02:35 -06:00
08b46af7be
add micro architecture for heterogeneous FPGA with single-mode DPRAM
2020-03-24 12:20:51 -06:00
9e4e12aae9
fixed echo message in the compression rate of gsb uniquifying
2020-03-22 16:13:04 -06:00
ff474d87de
fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs
2020-03-22 16:11:00 -06:00
fdf6a6bd3e
use chan_node_in_edges from rr_gsb in XML writer
2020-03-22 15:48:11 -06:00
3958ac2494
fix bugs in flow manager on default compress routing problems
2020-03-22 15:26:15 -06:00
fc6abc13fd
add physical tile utils to identify pins that have Fc=0
2020-03-21 21:02:47 -06:00
7b9384f3b2
add write_gsb command to shell interface
2020-03-21 19:40:26 -06:00
637be076dc
adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working
2020-03-21 18:49:20 -06:00
9a518e8bb6
bug fixed for tileable rr_graph builder for more 4x4 fabrics
2020-03-21 18:07:00 -06:00
63c4669dbb
fixed bug in the fast look-up for tileable rr_graph
2020-03-21 17:36:08 -06:00
c0e8d98c6f
bug fixed in tile direct builder
2020-03-21 12:43:56 -06:00
8f35f191eb
use the formalized function in FPGA-SDC to identify direct connection
2020-03-21 11:42:00 -06:00
28123b8052
remove the direct connected IPIN/OPIN from RR GSB builder
2020-03-21 11:38:39 -06:00
tangxifan