tangxifan
|
e1a7a2895a
|
simulation ini file name can be customizable
|
2019-11-02 09:59:34 -06:00 |
|
tangxifan
|
d5d7450ce7
|
make simulation ini writing as an option
|
2019-11-02 09:46:12 -06:00 |
|
tangxifan
|
ccabe4ce2a
|
refactoring Verilog formal verification top testbench using random vectors
|
2019-10-28 14:45:51 -06:00 |
AurelienUoU
|
a93d7e57f7
|
Scan chain support in directlist
|
2019-09-27 16:53:00 -06:00 |
|
tangxifan
|
edfa72a666
|
try to fix the bug in clock net identification
|
2019-08-13 16:47:28 -06:00 |
|
tangxifan
|
c7526cb43c
|
memory sanitized
|
2019-08-13 14:19:40 -06:00 |
|
tangxifan
|
392f579836
|
add linking functions for circuit models and architecture, memory sanitizing is ongoing
|
2019-08-13 13:25:23 -06:00 |
|
AurelienUoU
|
1cf4e78502
|
Update documentation and help
|
2019-07-15 21:16:15 -06:00 |
|
tangxifan
|
31749fe62b
|
fix bugs in fpga_flow.pl
|
2019-07-10 21:12:00 -06:00 |
Baudouin Chauviere
|
4ca0967453
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-09 14:35:51 -06:00 |
|
tangxifan
|
3077efa74f
|
add option to compact tileable routing arch
|
2019-07-04 17:13:34 -06:00 |
|
tangxifan
|
1a1da30ae9
|
fixed a critical bug in using tileable route chan W
|
2019-07-03 16:46:43 -06:00 |
|
tangxifan
|
4f3cb0bdf3
|
added tileable routing chanW adaption to fixed W router
|
2019-07-03 14:29:50 -06:00 |
|
tangxifan
|
0c3e8bb70a
|
add a new option to the router to enable conversion of route_chan_width to be tileable
|
2019-07-03 12:11:48 -06:00 |
|
tangxifan
|
95674c4687
|
added Switch Block SubType and SubFs for tileable rr_graph generation
|
2019-07-02 10:00:02 -06:00 |
|
Baudouin Chauviere
|
0ce9846e47
|
Stable, unfinished
|
2019-06-26 16:54:41 -06:00 |
|
tangxifan
|
59df305668
|
bug fixing and reorganize rr_graph builder source files
|
2019-06-23 16:40:13 -06:00 |
|
tangxifan
|
548242b368
|
plug-in tileable rr generator which can be enable by a XML property
|
2019-06-20 21:06:26 -06:00 |
|
AurelienUoU
|
ff00e4c79c
|
Free only if it's possible to free
|
2019-06-19 16:15:30 -06:00 |
|
tangxifan
|
44d21ebb90
|
fixed a bug in Verilog generator supporting SRAM5T
|
2019-06-13 14:42:39 -06:00 |
|
tangxifan
|
ca363da30c
|
add options to specify output directory of SB XML
|
2019-05-28 15:19:10 -06:00 |
|
Baudouin Chauviere
|
b48a27acf0
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-13 14:45:57 -06:00 |
|
Baudouin Chauviere
|
2019840d7c
|
cleaned unused variables
|
2019-05-13 14:45:02 -06:00 |
|
tangxifan
|
a3c3f2b892
|
developing compact routing hierarchy
|
2019-05-08 20:49:21 -06:00 |
|
AurelienUoU
|
42f20eda60
|
Add the user matching for internal register in formal verification script generation
|
2019-05-03 10:24:02 -06:00 |
|
tangxifan
|
46d44fa42a
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
tangxifan
|
72fbd8d6a8
|
update blif reader to identify clock signals
|
2018-12-10 13:28:44 -07:00 |
|
Aur??Lien ALACCHI
|
0580d8243f
|
Add Autochek testbench option
|
2018-12-08 17:19:12 -07:00 |
|
Baudouin Chauviere
|
b6bb419e1d
|
add a ModelSim option
|
2018-12-06 14:13:37 -07:00 |
|
Aur??Lien ALACCHI
|
9a8c7b391a
|
Add process for modelsim script autogeneration
|
2018-12-05 09:20:47 -07:00 |
|
Aur??Lien ALACCHI
|
8ac566ecc0
|
Add timing and initialization for simulation
|
2018-12-04 17:32:09 -07:00 |
|
tangxifan
|
c67ba5f58a
|
clean up codes
|
2018-09-27 14:26:08 -06:00 |
|
tangxifan
|
d683134b12
|
rename customized vpr7 to vpr7 XML to Production
|
2018-09-17 23:10:45 -06:00 |