Commit Graph

2443 Commits

Author SHA1 Message Date
tangxifan 73e2b857a3 add buffer support to FPGA-SPICE 2020-07-24 15:54:18 -06:00
tangxifan 021fedbc12 update fabric key to synchronize with new module/instance naming 2020-07-24 12:55:40 -06:00
tangxifan 2603836111 split logical tile netlists to keep good Verilog hierarchy 2020-07-24 12:53:21 -06:00
tangxifan be5966475e formulate file name, module name and instance name to be consistent 2020-07-24 12:23:27 -06:00
tangxifan fefcd88f14 update openfpga architecture README for power-gating 2020-07-22 21:55:59 -06:00
tangxifan 8a79ff2c24 deploy power gating test cases to CI 2020-07-22 20:22:59 -06:00
tangxifan 22159531c5 bug fix in power gating support of FPGA-Verilog 2020-07-22 20:21:38 -06:00
tangxifan ca867ea6fa add power gate inverter test case (full testbench) 2020-07-22 20:09:52 -06:00
tangxifan 87ef7f9f99 add power gate example architecture 2020-07-22 20:06:10 -06:00
tangxifan a4a38f8156 support multi-bit power gate ports in FPGA-SPICE 2020-07-22 20:04:39 -06:00
tangxifan f573fa3ee0 move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
2020-07-22 18:47:12 -06:00
tangxifan 97cca72590 add spice support on power gated inverters 2020-07-22 18:21:11 -06:00
tangxifan 8ade40713a add missing architecture for CI 2020-07-22 14:07:39 -06:00
tangxifan 1a1c3885e7 use k6 n10 in mux designs to speed up CI 2020-07-22 13:54:09 -06:00
tangxifan 95c1fe61e1 use k6 n8 in mux design to speed up CI 2020-07-22 13:49:03 -06:00
tangxifan f754c8af06 use k6_n10 architecture to reduce CI runtime 2020-07-22 13:45:55 -06:00
tangxifan 92c3449999 bug fix in the regression test due to benchmark changes 2020-07-22 13:17:05 -06:00
tangxifan 05dccadf21 bug fix in the testcases using yosys_vpr flow 2020-07-22 12:44:19 -06:00
tangxifan 7d39e136a4 enrich micro benchmarks 2020-07-22 12:33:52 -06:00
tangxifan 1d36de817f adapt generate bitstream testcase to use yosys vpr flow 2020-07-22 12:24:34 -06:00
tangxifan b96cdbf857 adapt preconfig test cases to use yosys_vpr flow 2020-07-22 12:23:39 -06:00
tangxifan d8804f4ec1 deploy yosys_vpr flow to basic regression tests 2020-07-22 12:21:59 -06:00
tangxifan f4e77e3bad Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2020-07-22 12:09:34 -06:00
ganeshgore 3b6cd885f3 BugFix: Fixed yosys_vpr with openFPGA_Shell 2020-07-22 11:57:04 -06:00
ganeshgore 226f1c703a Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev 2020-07-22 11:39:23 -06:00
tangxifan b5fd6aa859 add inverter subckt writer to FPGA-SPICE 2020-07-17 13:01:08 -06:00
tangxifan eb070694b5 fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture 2020-07-15 17:52:41 -06:00
tangxifan c26c268dcd update documentation on fast configuration support for configuration chain 2020-07-15 13:55:32 -06:00
Laboratory for Nano Integrated Systems (LNIS) ffc087336d
Merge pull request #68 from LNIS-Projects/dev
Remove obsolete documentation and add technology binding
2020-07-15 12:24:50 -06:00
tangxifan 7d1b524969 deploy fast configuration chain test case to CI 2020-07-15 11:57:12 -06:00
tangxifan ca90f337a7 add fast configuration chain test case 2020-07-15 11:56:47 -06:00
tangxifan 66a50742fc use configuration chain in the k4k4 test case to speed up CI 2020-07-15 11:56:11 -06:00
tangxifan 3f14fe62c7 add fast configuration support for configuration chain protocol 2020-07-15 11:44:23 -06:00
tangxifan 862d71f57a remove obselete vpr7 XML syntax from documentation 2020-07-15 11:13:47 -06:00
tangxifan cb0df2c1c6 update doc about technology binding between circuit library and device library 2020-07-15 11:05:33 -06:00
tangxifan de4586217f now device binding is not mandatory for circuit models 2020-07-14 12:04:22 -06:00
tangxifan e2b492f184 add circuit model tech binding 2020-07-13 20:35:10 -06:00
tangxifan 1c5bede282 update arch file with device technology binding information 2020-07-13 19:06:51 -06:00
Laboratory for Nano Integrated Systems (LNIS) cf9e412d84
Merge pull request #67 from LNIS-Projects/dev
hotfix on treating the dangling ports in pb_graph for analysis SDC ge…
2020-07-10 09:00:22 -06:00
tangxifan 1b55dfb441 hotfix on treating the dangling ports in pb_graph for analysis SDC generator 2020-07-09 23:28:42 -06:00
Laboratory for Nano Integrated Systems (LNIS) 3c77deb987
Merge pull request #66 from LNIS-Projects/docker
Updated Dockerfile for Ubuntu 18.04
2020-07-09 16:17:05 -06:00
tangxifan 2b4be83e0a
Merge pull request #64 from LNIS-Projects/dev
using a unified string to replace multi net names to save memory of b…
2020-07-09 10:10:33 -06:00
lnis 8037380659 . 2020-07-09 09:25:11 -06:00
tangxifan 62fd0947f5 using a unified string to replace multi net names to save memory of bitstream database 2020-07-08 16:28:20 -06:00
tangxifan c5f718b105
Merge pull request #63 from LNIS-Projects/dev
Improve runtime of fabric key loading; Documentation update for different file format of fabric keys
2020-07-07 11:16:32 -06:00
tangxifan 65dfc545c1 update documentation for fabric key 2020-07-07 10:28:29 -06:00
tangxifan 66e5e141a1 improve fabric key loader to reduce runtime 2020-07-07 10:19:34 -06:00
tangxifan f246da6538
Merge pull request #62 from LNIS-Projects/dev
Simplify fabric key where users just need to provide alias; start porting FPGA-SPICE
2020-07-06 18:01:20 -06:00
tangxifan 7615db2be6 update documentation for the new fabric key rules 2020-07-06 16:44:21 -06:00
tangxifan 824b56f14c fabric key can now accept instance name only; decoders are no longer part of the key 2020-07-06 16:42:33 -06:00