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Merge pull request #64 from LNIS-Projects/dev 

using a unified string to replace multi net names to save memory of b…
This commit is contained in:
tangxifan 2020-07-09 10:10:33 -06:00 committed by GitHub
parent c5f718b105 62fd0947f5
commit 2b4be83e0a
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GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 89 additions and 54 deletions
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24
libopenfpga/libfpgabitstream/src/bitstream_manager.cpp
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@ -123,14 +123,14 @@ int BitstreamManager::block_path_id(const ConfigBlockId& block_id) const {
return block_path_ids_[block_id];
}
std::vector<std::string> BitstreamManager::block_input_net_ids(const ConfigBlockId& block_id) const {
std::string BitstreamManager::block_input_net_ids(const ConfigBlockId& block_id) const {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block_id));
return block_input_net_ids_[block_id];
}
std::vector<std::string> BitstreamManager::block_output_net_ids(const ConfigBlockId& block_id) const {
std::string BitstreamManager::block_output_net_ids(const ConfigBlockId& block_id) const {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block_id));
@ -246,29 +246,13 @@ void BitstreamManager::add_path_id_to_block(const ConfigBlockId& block, const in
block_path_ids_[block] = path_id;
}
void BitstreamManager::reserve_block_input_net_ids(const ConfigBlockId& block,
const size_t& num_input_net_ids) {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block));
block_input_net_ids_[block].reserve(num_input_net_ids);
}
void BitstreamManager::add_input_net_id_to_block(const ConfigBlockId& block,
const std::string& input_net_id) {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block));
/* Add the bit to the block */
block_input_net_ids_[block].push_back(input_net_id);
}
void BitstreamManager::reserve_block_output_net_ids(const ConfigBlockId& block,
const size_t& num_output_net_ids) {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block));
block_output_net_ids_[block].reserve(num_output_net_ids);
block_input_net_ids_[block] = input_net_id;
}
void BitstreamManager::add_output_net_id_to_block(const ConfigBlockId& block,
@ -277,7 +261,7 @@ void BitstreamManager::add_output_net_id_to_block(const ConfigBlockId& block,
VTR_ASSERT(true == valid_block_id(block));
/* Add the bit to the block */
block_output_net_ids_[block].push_back(output_net_id);
block_output_net_ids_[block] = output_net_id;
}
/******************************************************************************

14
libopenfpga/libfpgabitstream/src/bitstream_manager.h
View File

@ -138,10 +138,10 @@ class BitstreamManager {
int block_path_id(const ConfigBlockId& block_id) const;
/* Find input net ids of a block */
std::vector<std::string> block_input_net_ids(const ConfigBlockId& block_id) const;
std::string block_input_net_ids(const ConfigBlockId& block_id) const;
/* Find input net ids of a block */
std::vector<std::string> block_output_net_ids(const ConfigBlockId& block_id) const;
std::string block_output_net_ids(const ConfigBlockId& block_id) const;
public: /* Public Mutators */
/* Add a new configuration bit to the bitstream manager */
@ -177,15 +177,9 @@ class BitstreamManager {
/* Add a path id to a block */
void add_path_id_to_block(const ConfigBlockId& block, const int& path_id);
/* Reserve input net ids for a block */
void reserve_block_input_net_ids(const ConfigBlockId& block, const size_t& num_input_net_ids);
/* Add an input net id to a block */
void add_input_net_id_to_block(const ConfigBlockId& block, const std::string& input_net_id);
/* Reserve output net ids for a block */
void reserve_block_output_net_ids(const ConfigBlockId& block, const size_t& num_output_net_ids);
/* Add an output net id to a block */
void add_output_net_id_to_block(const ConfigBlockId& block, const std::string& output_net_id);
@ -233,8 +227,8 @@ class BitstreamManager {
* -Bitstream manager will NOT check if the id is good for bitstream builders
* It just store the results
*/
vtr::vector<ConfigBlockId, std::vector<std::string>> block_input_net_ids_;
vtr::vector<ConfigBlockId, std::vector<std::string>> block_output_net_ids_;
vtr::vector<ConfigBlockId, std::string> block_input_net_ids_;
vtr::vector<ConfigBlockId, std::string> block_output_net_ids_;
/* Unique id of a bit in the Bitstream */
size_t num_bits_;

18
libopenfpga/libfpgabitstream/src/read_xml_arch_bitstream.cpp
View File

@ -62,9 +62,16 @@ void rec_read_xml_bitstream_block(pugi::xml_node& xml_bitstream_block,
input_nets[id] = net_name;
}
std::string input_nets_str;
bool need_splitter = false;
for (const std::string& input_net : input_nets) {
bitstream_manager.add_input_net_id_to_block(curr_block, input_net);
if (true == need_splitter) {
input_nets_str += std::string(" ");
}
input_nets_str += input_net;
need_splitter = true;
}
bitstream_manager.add_input_net_id_to_block(curr_block, input_nets_str);
}
/* Parse output nets if defined */
@ -86,9 +93,16 @@ void rec_read_xml_bitstream_block(pugi::xml_node& xml_bitstream_block,
output_nets[id] = net_name;
}
std::string output_nets_str;
bool need_splitter = false;
for (const std::string& output_net : output_nets) {
bitstream_manager.add_output_net_id_to_block(curr_block, output_net);
if (true == need_splitter) {
output_nets_str += std::string(" ");
}
output_nets_str += output_net;
need_splitter = true;
}
bitstream_manager.add_output_net_id_to_block(curr_block, output_nets_str);
}
/* Parse configuration bits */

9
libopenfpga/libfpgabitstream/src/write_xml_arch_bitstream.cpp
View File

@ -13,6 +13,7 @@
/* Headers from openfpgautil library */
#include "openfpga_digest.h"
#include "openfpga_tokenizer.h"
#include "openfpga_reserved_words.h"
@ -95,7 +96,9 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp,
write_tab_to_file(fp, hierarchy_level + 1);
fp << "<input_nets>\n";
size_t path_counter = 0;
for (const std::string& net : bitstream_manager.block_input_net_ids(block)) {
/* Split with space */
StringToken input_net_tokenizer(bitstream_manager.block_input_net_ids(block));
for (const std::string& net : input_net_tokenizer.split(std::string(" "))) {
write_tab_to_file(fp, hierarchy_level + 2);
fp << "<path id=\"" << path_counter << "\"";
fp << " net_name=\"";
@ -113,7 +116,9 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp,
write_tab_to_file(fp, hierarchy_level + 1);
fp << "<output_nets>\n";
size_t path_counter = 0;
for (const std::string& net : bitstream_manager.block_output_net_ids(block)) {
/* Split with space */
StringToken output_net_tokenizer(bitstream_manager.block_output_net_ids(block));
for (const std::string& net : output_net_tokenizer.split(std::string(" "))) {
write_tab_to_file(fp, hierarchy_level + 2);
fp << "<path id=\"" << path_counter << "\"";
fp << " net_name=\"";

29
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -214,20 +214,33 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag
bitstream_manager.add_block_bits(mux_mem_block, mux_bitstream);
/* Record path ids, input and output nets */
bitstream_manager.add_path_id_to_block(mux_mem_block, mux_input_pin_id);
bitstream_manager.reserve_block_input_net_ids(mux_mem_block, input_nets.size());
/* Add input nets */
std::string input_net_ids;
bool need_splitter = false;
for (const AtomNetId& input_net : input_nets) {
if (true == atom_ctx.nlist.valid_net_id(input_net)) {
bitstream_manager.add_input_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(input_net));
} else {
bitstream_manager.add_input_net_id_to_block(mux_mem_block, std::string("unmapped"));
/* Add a space as a splitter*/
if (true == need_splitter) {
input_net_ids += std::string(" ");
}
if (true == atom_ctx.nlist.valid_net_id(input_net)) {
input_net_ids += atom_ctx.nlist.net_name(input_net);
} else {
input_net_ids += std::string("unmapped");
}
need_splitter = true;
}
bitstream_manager.add_input_net_id_to_block(mux_mem_block, input_net_ids);
/* Add output nets */
std::string output_net_ids;
if (true == atom_ctx.nlist.valid_net_id(output_net)) {
bitstream_manager.reserve_block_output_net_ids(mux_mem_block, 1);
bitstream_manager.add_output_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(output_net));
output_net_ids += atom_ctx.nlist.net_name(output_net);
} else {
bitstream_manager.add_output_net_id_to_block(mux_mem_block, std::string("unmapped"));
output_net_ids += std::string("unmapped");
}
bitstream_manager.add_output_net_id_to_block(mux_mem_block, output_net_ids);
break;
}

49
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
View File

@ -102,22 +102,34 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager,
bitstream_manager.add_block_bits(mux_mem_block, mux_bitstream);
/* Record path ids, input and output nets */
bitstream_manager.add_path_id_to_block(mux_mem_block, path_id);
bitstream_manager.reserve_block_input_net_ids(mux_mem_block, input_nets.size());
/* Add input nets */
bool need_splitter = false;
std::string input_net_ids;
for (const ClusterNetId& input_net : input_nets) {
/* Add a space as a splitter*/
if (true == need_splitter) {
input_net_ids += std::string(" ");
}
AtomNetId input_atom_net = atom_ctx.lookup.atom_net(input_net);
if (true == atom_ctx.nlist.valid_net_id(input_atom_net)) {
bitstream_manager.add_input_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(input_atom_net));
input_net_ids += atom_ctx.nlist.net_name(input_atom_net);
} else {
bitstream_manager.add_input_net_id_to_block(mux_mem_block, std::string("unmapped"));
input_net_ids += std::string("unmapped");
}
need_splitter = true;
}
bitstream_manager.add_input_net_id_to_block(mux_mem_block, input_net_ids);
/* Add output nets */
std::string output_net_ids;
AtomNetId output_atom_net = atom_ctx.lookup.atom_net(output_net);
bitstream_manager.reserve_block_output_net_ids(mux_mem_block, 1);
if (true == atom_ctx.nlist.valid_net_id(output_atom_net)) {
bitstream_manager.add_output_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(output_atom_net));
output_net_ids += atom_ctx.nlist.net_name(output_atom_net);
} else {
bitstream_manager.add_output_net_id_to_block(mux_mem_block, std::string("unmapped"));
output_net_ids += std::string("unmapped");
}
bitstream_manager.add_output_net_id_to_block(mux_mem_block, output_net_ids);
}
/********************************************************************
@ -291,22 +303,35 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager,
bitstream_manager.add_block_bits(mux_mem_block, mux_bitstream);
/* Record path ids, input and output nets */
bitstream_manager.add_path_id_to_block(mux_mem_block, path_id);
bitstream_manager.reserve_block_input_net_ids(mux_mem_block, input_nets.size());
/* Add input nets */
bool need_splitter = false;
std::string input_net_ids;
for (const ClusterNetId& input_net : input_nets) {
/* Add a space as a splitter*/
if (true == need_splitter) {
input_net_ids += std::string(" ");
}
AtomNetId input_atom_net = atom_ctx.lookup.atom_net(input_net);
if (true == atom_ctx.nlist.valid_net_id(input_atom_net)) {
bitstream_manager.add_input_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(input_atom_net));
input_net_ids += atom_ctx.nlist.net_name(input_atom_net);
} else {
bitstream_manager.add_input_net_id_to_block(mux_mem_block, std::string("unmapped"));
input_net_ids += std::string("unmapped");
}
need_splitter = true;
}
bitstream_manager.add_input_net_id_to_block(mux_mem_block, input_net_ids);
/* Add output nets */
std::string output_net_ids;
AtomNetId output_atom_net = atom_ctx.lookup.atom_net(output_net);
bitstream_manager.reserve_block_output_net_ids(mux_mem_block, 1);
if (true == atom_ctx.nlist.valid_net_id(output_atom_net)) {
bitstream_manager.add_output_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(output_atom_net));
output_net_ids += atom_ctx.nlist.net_name(output_atom_net);
} else {
bitstream_manager.add_output_net_id_to_block(mux_mem_block, std::string("unmapped"));
output_net_ids += std::string("unmapped");
}
bitstream_manager.add_output_net_id_to_block(mux_mem_block, output_net_ids);
}
/********************************************************************