tangxifan
1a2c66f07d
[Architecture] Add openfpga architecture where frame-based configuration procotol uses a SRAM cell
2020-09-23 17:34:49 -06:00
tangxifan
a3c982a83f
[Architecture] Patch the openfpga architecture using active-low configurable latch
2020-09-23 17:27:16 -06:00
tangxifan
893859be37
[Architecture] Add openfpga architecture using active-low configurable latch
2020-09-23 17:21:00 -06:00
tangxifan
1aab691e9d
[Architecture] Add openfpga architecture using pattern based local routing
2020-09-23 16:06:16 -06:00
tangxifan
72749be4bd
[Architecture] Add OpenFPGA architecture for k4n4 with fracturable 32-bit multiplier
2020-09-22 15:31:34 -06:00
tangxifan
13df6c1c21
[Architecture] Add openfpga architecture for k4n4 using multiple segments
2020-09-22 12:36:11 -06:00
tangxifan
26fba4a94b
[Architecture] Add openfpga architectue for k4n4 with bram blocks
2020-09-22 12:22:59 -06:00
tangxifan
dd192a2f54
[Architecture] Add a k4k4 openfpga architecture with carry chain for quick test
2020-09-22 11:34:23 -06:00
tangxifan
60f328a2ab
[Architecture] Add openfpga architecture for a small k4 fracturable FPGA
2020-09-21 17:36:57 -06:00
tangxifan
f5b7ac6269
[OpenFPGA Architecture] Add a new architecture with no local routing
2020-09-16 18:04:55 -06:00
tangxifan
aaf63050bb
[OpenFPGA architecture] Add the architecture where routing multiplexers have only output buffers
2020-09-14 15:58:34 -06:00
tangxifan
aa9521b23b
[OpenFPGA architecture] Add the architecture where routing multiplexers have only input buffers
2020-09-14 15:57:44 -06:00
tangxifan
eecfd186f0
[OpenFPGA Architecture] Add the openfpga architecture for multiplexers without buffers
2020-09-14 15:46:10 -06:00
tangxifan
4b3142c4ee
[Architecture File] Patch openfpga architecture with default circuit model definition
2020-08-23 15:13:28 -06:00
tangxifan
9101ba1021
[Architecture Language] Update openfpga architecture files for default models
2020-08-23 14:55:44 -06:00
tangxifan
18735894f9
bug fix in openfpga arch: data1 and out1 should have the same offset as the data2 and out2
2020-08-19 15:27:30 -06:00
tangxifan
aa4a9b28cc
start testing the initial offset in the flagship architecture
2020-08-19 15:03:46 -06:00
tangxifan
f64079641d
bug fix in flagship vpr arch with frac mem and dsp
2020-08-19 12:43:58 -06:00
tangxifan
42b5ea2cb1
bug fix in openfpga arch for frac mem and dsp
2020-08-18 20:42:36 -06:00
tangxifan
098859fe06
bug fix in the frac memory & DSP architecture
2020-08-18 15:05:51 -06:00
tangxifan
f833e0ec66
add a flagship architecture using fracturable memory and dsp
2020-08-17 17:49:51 -06:00
tangxifan
fefcd88f14
update openfpga architecture README for power-gating
2020-07-22 21:55:59 -06:00
tangxifan
22159531c5
bug fix in power gating support of FPGA-Verilog
2020-07-22 20:21:38 -06:00
tangxifan
87ef7f9f99
add power gate example architecture
2020-07-22 20:06:10 -06:00
tangxifan
8ade40713a
add missing architecture for CI
2020-07-22 14:07:39 -06:00
tangxifan
f754c8af06
use k6_n10 architecture to reduce CI runtime
2020-07-22 13:45:55 -06:00
tangxifan
eb070694b5
fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
2020-07-15 17:52:41 -06:00
tangxifan
66a50742fc
use configuration chain in the k4k4 test case to speed up CI
2020-07-15 11:56:11 -06:00
tangxifan
1c5bede282
update arch file with device technology binding information
2020-07-13 19:06:51 -06:00
tangxifan
73e75bf456
add readme for OpenFPGA architecture naming
2020-07-01 10:27:21 -06:00
tangxifan
60dd37e086
remove simulation settings from openfpga arch XML
...
update travis to split CI tests
fix errors in travis configuration
fixing travis errors in scripts
keep fixing travis
fix travis on build.sh
bug fixing in travis CI
bug fix in travis regression test run
fixing bugs in the travis scripts
bug fix in travis script: remove common.sh in regression test call
keep bug fixing in travis
2020-06-11 19:31:17 -06:00
tangxifan
baa2c6b7ef
update arch to support reset signal for SRAm
2020-06-11 19:31:14 -06:00
tangxifan
aac2e8c805
update openfpga architecture for memory bank usage
2020-06-11 19:31:14 -06:00
tangxifan
a1ec6833c2
add memory bank example arch xml
2020-06-11 19:31:13 -06:00
tangxifan
8b5b221a21
add new architecture for standalone memory organization
2020-06-11 19:31:12 -06:00
tangxifan
6a72c66eb8
bug fixed for frame-based configuration memory in top-level full testbench
2020-06-11 19:31:11 -06:00
tangxifan
3fa3b17061
start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches.
2020-06-11 19:31:10 -06:00
tangxifan
4083fae41a
add new test cases about user-defined simulation settings
2020-06-11 19:31:03 -06:00
tangxifan
2fbf9c2cfc
change to a higher simulation clock speed to accelerate CI verification.
...
Later, we should place simulation information in another XML so that we can reuse that easily
2020-06-11 19:31:03 -06:00
tangxifan
889bc8dbe8
add more test cases about LUT design and deploy to CI
2020-06-11 19:31:02 -06:00
tangxifan
889f179ce7
add local encoder test case
2020-06-11 19:31:01 -06:00
tangxifan
73e9006372
add arch file with spy pads
2020-04-22 12:56:09 -06:00
tangxifan
f6b7583a2a
add tasks for single mode
2020-04-20 12:55:40 -06:00
tangxifan
f76a3090c4
add mcnc big20 test cases and start debugging
2020-04-18 19:25:16 -06:00
tangxifan
2ffd174e6a
fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
2020-04-15 15:48:33 -06:00
tangxifan
23aef96d3a
add behavioral verilog test case to Travis CI
2020-04-12 19:55:47 -06:00
tangxifan
f71a85a1d4
add test cases on different routing multiplexer circuit designs to Travis CI
2020-04-12 15:39:45 -06:00
tangxifan
214d98fbcd
add register chain and scan chain to Travis CI
2020-04-12 15:28:22 -06:00
tangxifan
da5af8f0e0
try to add aib test case. bug found
2020-04-12 14:54:45 -06:00
tangxifan
600a48edc7
add test case of BRAM to Travis CI
2020-04-12 14:27:05 -06:00