tangxifan
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62497549b6
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[HDL] Add multi-mode DFF module
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2021-04-21 20:04:40 -06:00 |
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tangxifan
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3a5c26c6a1
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[Test] Update IWLS test by using new architecture and customize DFF techmap
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2021-04-21 19:51:25 -06:00 |
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tangxifan
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8cbea6a268
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[HDL] Add technology library for customizable DFF synthesis
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2021-04-21 19:50:51 -06:00 |
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tangxifan
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3d615e1516
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[Script] Add yosys script supporting customize DFF/BRAM/DSP mapping
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2021-04-21 19:50:07 -06:00 |
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tangxifan
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9d9840d9b7
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[Arch] Add architecture using multi-mode DFFs
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2021-04-21 19:49:48 -06:00 |
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tangxifan
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8046b16c15
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[Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing
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2021-04-21 14:04:34 -06:00 |
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tangxifan
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b203ef7bc2
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[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs
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2021-04-21 14:03:51 -06:00 |
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tangxifan
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2fa370d7d5
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[Test] Patch regression tests for fpga bitstream
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2021-04-19 17:15:14 -06:00 |
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tangxifan
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64163edbe6
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[Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting
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2021-04-19 16:15:25 -06:00 |
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tangxifan
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578d81b67a
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[Test] Patch task configuration file
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2021-04-19 16:15:00 -06:00 |
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tangxifan
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18eb5c9de9
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[Test] Deploy new test to CI
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2021-04-19 15:56:41 -06:00 |
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tangxifan
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5976cc0a1c
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[Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection
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2021-04-19 15:54:18 -06:00 |
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tangxifan
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7018073e28
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[Script] Update openfpga shell script w/o ace usage to adapt pin constraint files
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2021-04-17 15:04:51 -06:00 |
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tangxifan
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da95da933b
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[Test] Add pin constraint file to map reset to correct FPGA pins
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2021-04-17 15:04:26 -06:00 |
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tangxifan
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e3dafe99da
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[Arch] Revert to old version arch due to editing by mistake
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2021-04-16 20:58:32 -06:00 |
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tangxifan
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c020333512
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Merge branch 'master' into dff_techmap
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2021-04-16 20:54:28 -06:00 |
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tangxifan
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7172fc9ea1
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[Test] Patch test for architecture using asynchronous DFFs
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2021-04-16 20:48:37 -06:00 |
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tangxifan
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0a15f366cb
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[HDL] Patch dff models used in yosys tech map
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2021-04-16 20:48:15 -06:00 |
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tangxifan
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16e02ef485
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[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
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2021-04-16 20:47:39 -06:00 |
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tangxifan
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1c2f91b7e6
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[Script] Patch yosys script with dff tech map
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2021-04-16 20:47:18 -06:00 |
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tangxifan
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2666726f36
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[Script] Remove clock routing from example openfpga shell script without ace
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2021-04-16 20:46:49 -06:00 |
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tangxifan
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23d08757cf
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[Script] Add example script without using ACE2
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2021-04-16 20:20:10 -06:00 |
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tangxifan
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bbdc0e53af
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[Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures
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2021-04-16 20:14:48 -06:00 |
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tangxifan
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b11d03f9c5
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[Test] Deploy new test to CI
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2021-04-16 20:01:40 -06:00 |
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tangxifan
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93be81abe1
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[Test] Add test case for architecture using DFF with reset
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2021-04-16 20:00:48 -06:00 |
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tangxifan
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5414a6a3da
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[Script] Add yosys script with custom DFF tech mapping
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2021-04-16 20:00:30 -06:00 |
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tangxifan
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4239bb4e68
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[Arch] Patch architecture files using multi-mode DFFs
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2021-04-16 19:59:55 -06:00 |
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tangxifan
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f2f7f010ea
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[Arch] Add new architectures using DFF with reset in VPR
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2021-04-16 19:26:18 -06:00 |
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tangxifan
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64294ae4eb
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[Doc] Update README for architecture files due to new architecture features
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2021-04-16 19:25:54 -06:00 |
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tangxifan
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ff4460695b
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[HDL] Add dff tech map files for yosys
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2021-04-16 17:00:55 -06:00 |
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tangxifan
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e46c6e75a3
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[Benchmark] Add missing RTL for IWLS2005 benchmarks
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2021-04-16 16:50:41 -06:00 |
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tangxifan
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87587bbb74
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[Test] Add iwls2005 benchmarks to regression tests
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2021-04-16 16:12:05 -06:00 |
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tangxifan
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1566a5558a
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[Test] Add task configuration file for iwls2005
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2021-04-16 16:10:31 -06:00 |
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tangxifan
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43bf016576
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[Script] Add example openfpga shell script for iwls benchmark
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2021-04-16 16:09:47 -06:00 |
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tangxifan
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26d3b5a954
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[Benchmark] Reorganize iwls2005 benchmark: separate the location of rtl and testbenches
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2021-04-16 16:08:58 -06:00 |
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tangxifan
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86ad572530
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[Benchmark] Add opencore RTLs from IWLS 2005 benchmarks
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2021-04-16 14:27:54 -06:00 |
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tangxifan
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b469705819
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Merge branch 'master' into fpga_sdc_test
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2021-04-11 21:14:46 -06:00 |
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tangxifan
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1db8bd7eec
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[Test] Update regression test with new SDC tests
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2021-04-11 20:24:32 -06:00 |
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tangxifan
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07f6066c11
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[Script] Update timing unit in SDC example script
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2021-04-11 20:24:18 -06:00 |
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tangxifan
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94c4c817eb
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[Test] Expand sdc time unit test to sweep all the available units
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2021-04-11 20:14:09 -06:00 |
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tangxifan
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a4893e27cf
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[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
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2021-04-11 17:26:27 -06:00 |
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tangxifan
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44d97ead86
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Merge branch 'master' into hetergeneous_arch
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2021-03-23 17:05:03 -06:00 |
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tangxifan
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b00b4f0f5f
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[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian
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2021-03-23 15:44:53 -06:00 |
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tangxifan
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d82ffe0cbf
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[Test] Deploy MAC_8 benchmark to regression test
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2021-03-23 15:36:28 -06:00 |
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tangxifan
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108c84a022
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[HDL] Add HDL for 8-bit single-mode multiplier
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2021-03-23 15:36:09 -06:00 |
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tangxifan
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145a80de43
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[Script] Add an openfpga shell script for heterogeneous fpga verification
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2021-03-23 15:35:34 -06:00 |
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tangxifan
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fdec72b5bc
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[Arch] Add an example architecture with 8-bit single-mode multiplier
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2021-03-23 15:35:06 -06:00 |
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tangxifan
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be03eafd66
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[Benchmark] Add a micro benchmark: 8-bit multiply and accumulate
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2021-03-23 15:33:37 -06:00 |
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tangxifan
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8c970a792a
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[Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier
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2021-03-23 15:33:00 -06:00 |
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tangxifan
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6b0409da60
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[Script] Add a template yosys script support only DSP mapping
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2021-03-23 15:32:10 -06:00 |