tangxifan
|
a4bbffd1aa
|
[HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA
|
2021-03-23 15:30:41 -06:00 |
|
tangxifan
|
fff16a01ab
|
[Test] Update tolerance when checking VTR benchmark QoR
|
2021-03-23 12:27:20 -06:00 |
|
tangxifan
|
781880ed93
|
[Script] Add tolerance options to check qor script
|
2021-03-23 12:26:33 -06:00 |
|
tangxifan
|
e3f8a6cf7a
|
[Test] Deploy QoR check to VTR benchmark regression test
|
2021-03-23 11:15:22 -06:00 |
|
tangxifan
|
351dec5935
|
[Test] Add QoR csv file for vtr benchmarks
|
2021-03-23 11:15:02 -06:00 |
|
tangxifan
|
23e7f7f1f5
|
[Script] Update default list of result extraction for openfpga flow
|
2021-03-23 11:06:42 -06:00 |
|
tangxifan
|
adfbd28a7a
|
[Script] Add a simple QoR checker
|
2021-03-23 11:06:16 -06:00 |
|
tangxifan
|
61eddb08de
|
[Test] Update task configuration by commenting out high-runtime VTR benchmarks
|
2021-03-22 14:42:42 -06:00 |
|
tangxifan
|
55d1004cf2
|
[Benchmark] Add missing DPRAM module to LU32PEEng
|
2021-03-22 14:41:38 -06:00 |
|
tangxifan
|
5fc83ebea3
|
[Benchmark] Add missing DPRAM modules to LU8PEEng
|
2021-03-22 14:38:00 -06:00 |
|
tangxifan
|
b828f91a78
|
[Benchmark] Add missing DPRAM and SPRAM modules to mcml
|
2021-03-22 14:13:05 -06:00 |
|
tangxifan
|
d050f1b746
|
[Script] Enable fast bitstream generation for VTR benchmarks
|
2021-03-22 12:54:36 -06:00 |
|
tangxifan
|
4bfd0c0a02
|
[Test] Enable more VTR benchmark in testing
|
2021-03-22 12:53:30 -06:00 |
|
tangxifan
|
b906ab814e
|
[Benchmark] Add missing DPRAM module to mkPktMerge
|
2021-03-22 12:51:23 -06:00 |
|
tangxifan
|
310c2a9495
|
[Benchmark] Add missing DPRAM module to mkDelayWorker32B
|
2021-03-22 12:51:02 -06:00 |
|
tangxifan
|
707247283c
|
[Benchmark] Add missing DPRAM module to mkSMAdapter4B
|
2021-03-22 12:50:39 -06:00 |
|
tangxifan
|
eb056e2afd
|
[Benchmark] Add missing DPRAM module to or1200
|
2021-03-22 12:50:17 -06:00 |
|
tangxifan
|
7fd345a616
|
[Script] Solved the problem on BRAM mapping in the yosys script supporting both DSP and BRAMs
|
2021-03-22 10:39:47 -06:00 |
|
tangxifan
|
cc10b10703
|
[Test] Enable more benchmarks for testing; See problems when mapping BRAMs
|
2021-03-20 22:53:37 -06:00 |
|
tangxifan
|
169ee53b79
|
[Benchmark] Add missing modules to VTR benchmarks
|
2021-03-20 22:53:17 -06:00 |
|
tangxifan
|
eca2a35612
|
[Script] Add route chan width option to vtr openfpga script
|
2021-03-20 22:00:09 -06:00 |
|
tangxifan
|
9a3aff274f
|
[Test] Use fix routing channel width to save runtime for VTR benchmarks
|
2021-03-20 21:59:44 -06:00 |
|
tangxifan
|
ca9a70fc88
|
[Test] Comment out benchmarks have problems in synthesis
|
2021-03-20 21:29:21 -06:00 |
|
tangxifan
|
125e94a6b3
|
[Test] Add full VTR benchmark (with most commented); ready for massive testing
|
2021-03-20 21:01:18 -06:00 |
|
tangxifan
|
2bd8ef2af9
|
[Benchmark] Patch boundtop.v with missing SPRAM module
|
2021-03-20 21:00:53 -06:00 |
|
tangxifan
|
cb07848475
|
[Script] Remove verilog and SDC generation from vtr benchmark openfpga script; Focus on bitstream generation
|
2021-03-20 18:11:54 -06:00 |
|
tangxifan
|
f3792bc6f6
|
[Test] Update VTR benchmark test case to include DSP example benchmark
|
2021-03-20 18:09:19 -06:00 |
|
tangxifan
|
477a522885
|
[HDL] Rename tech lib to be consistent with arch name changes
|
2021-03-20 18:08:03 -06:00 |
|
tangxifan
|
911979a731
|
[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
|
2021-03-20 18:04:59 -06:00 |
|
tangxifan
|
1185f7b8bf
|
[Script] Add a template yosys script to enable DSP mapping
|
2021-03-20 17:05:30 -06:00 |
|
tangxifan
|
6bf4880c50
|
[benchmark] Add vtr benchmark
|
2021-03-17 15:24:26 -06:00 |
|
tangxifan
|
f9dc7c1b54
|
[HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells
|
2021-03-17 15:15:22 -06:00 |
|
tangxifan
|
08a86e056a
|
[Test] Add vtr benchmark regression test
|
2021-03-17 15:13:58 -06:00 |
|
tangxifan
|
7eeb35d21f
|
[Script] Bug fix in yosys script to synthesis BRAM
|
2021-03-17 15:12:04 -06:00 |
|
tangxifan
|
1976a8068f
|
[Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added)
|
2021-03-17 15:11:17 -06:00 |
|
tangxifan
|
deee7ba366
|
[Script] Add example script to run vtr benchmarks
|
2021-03-17 15:10:56 -06:00 |
|
tangxifan
|
910f8471dd
|
[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
|
2021-03-17 15:10:05 -06:00 |
|
tangxifan
|
76113a80fa
|
[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture
|
2021-03-17 15:09:12 -06:00 |
|
tangxifan
|
e1f8b252b1
|
Merge branch 'master' into yosys_heterogeneous_block_support
|
2021-03-16 20:05:21 -06:00 |
|
tangxifan
|
d12a8a03fd
|
[Test] Update test case using yosys bram parameters
|
2021-03-16 19:52:17 -06:00 |
|
tangxifan
|
094b3e9b90
|
[Script] Use parameters in template yosys script supporting BRAMs
|
2021-03-16 19:51:48 -06:00 |
|
tangxifan
|
cea43c2c45
|
[HDL] Add SPRAM module to generic yosys tech lib for openfpga usage
|
2021-03-16 18:04:31 -06:00 |
|
tangxifan
|
73b06256d0
|
[Test] Deploy the new yosys script supporting BRAM to regression tests
|
2021-03-16 16:52:59 -06:00 |
|
tangxifan
|
84778bd38d
|
[Script] Add new yosys script to support architectures with BRAMs
|
2021-03-16 16:52:18 -06:00 |
|
tangxifan
|
090f483a11
|
[Script] Now task-run script support the use of env variables openfpga_path in yosys scripts
|
2021-03-16 16:45:57 -06:00 |
|
tangxifan
|
76837e02e6
|
[Script] Rename yosys script supporting bram and restructure techlib files
|
2021-03-16 16:16:53 -06:00 |
|
tangxifan
|
e61857aa2b
|
Merge branch 'master' into ganesh_dev
|
2021-03-11 19:17:02 -07:00 |
|
tangxifan
|
366bec232c
|
[Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI
|
2021-03-11 15:25:48 -07:00 |
|
tangxifan
|
bb2a02c9ad
|
[HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v]
|
2021-03-11 15:23:14 -07:00 |
|
tangxifan
|
baf162e401
|
[Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification
|
2021-03-10 22:45:19 -07:00 |
|
tangxifan
|
a6186db315
|
[Test] Update bitstream annotation with new syntax
|
2021-03-10 20:45:17 -07:00 |
|
tangxifan
|
7d07f5d8cb
|
[Test] Update bitstream setting example with mode bit overwriting
|
2021-03-10 15:34:53 -07:00 |
|
tangxifan
|
b42541d84e
|
[Flow] Support multiple iterations in rewriting yosys scripts
|
2021-03-10 14:10:35 -07:00 |
|
tangxifan
|
90a00da1df
|
[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'
|
2021-03-10 13:56:35 -07:00 |
|
tangxifan
|
d21909ad6c
|
[Test] Use custom rewriting script in lut_adder test
|
2021-03-10 13:48:20 -07:00 |
|
tangxifan
|
0e772bc3b4
|
[Script] Patch the yosys rewrite script to avoid existing blif outputs
|
2021-03-10 13:47:30 -07:00 |
|
tangxifan
|
7adb78b159
|
[Script] Add a template yosys script with rewriting at the end
|
2021-03-10 13:40:31 -07:00 |
|
tangxifan
|
035043d0d8
|
[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr
|
2021-03-10 13:36:11 -07:00 |
|
tangxifan
|
5d46537b5b
|
[Script] Allow users to specify custom post-synthesis verilog for simulation
|
2021-03-10 11:45:55 -07:00 |
|
tangxifan
|
aafd87c3f9
|
[Flow] Update flow-run to support custom yosys rewrite scripts
|
2021-03-10 11:36:29 -07:00 |
Tarachand Pagarani
|
db8ea86b2f
|
update tests to use no_ff_map and remove tests that need async set/reset for now
|
2021-03-10 10:04:45 -08:00 |
|
Tarachand Pagarani
|
608bd1f658
|
comment out desings that utilize local async reset/preset
|
2021-03-09 19:24:01 -08:00 |
|
Tarachand Pagarani
|
7f4c20ff33
|
comment out desings that utilize local async reset/preset
|
2021-03-09 10:37:06 -08:00 |
|
Tarachand Pagarani
|
c4b83aeaa9
|
bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type
|
2021-03-09 00:46:40 -08:00 |
|
tangxifan
|
2daa770319
|
[Arch] Update openfpga architecture to include quicklogic cell sim
|
2021-03-08 21:40:29 -07:00 |
|
tangxifan
|
812d8c950e
|
[Script] Update quicklogic's script to output correct verilog file name
|
2021-03-08 21:39:44 -07:00 |
|
tangxifan
|
37aa42d305
|
[Test] Patch task configuration file for lut_adder_test to use correct rewrite script
|
2021-03-08 21:38:51 -07:00 |
|
tangxifan
|
c53c41b7a5
|
[Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file
|
2021-03-08 21:09:23 -07:00 |
|
tangxifan
|
131643dcc0
|
[Flow] Bug fix for yosys rewrite function in openfpga flow-run script
|
2021-03-08 21:08:55 -07:00 |
ganeshgore
|
b860722893
|
Fixed parameter ys_rewrite_params name bug
|
2021-03-08 10:34:39 -07:00 |
|
ganeshgore
|
52de55e7eb
|
Merge branch 'master' into ganesh_dev
|
2021-03-08 10:15:06 -07:00 |
|
tangxifan
|
906d2fa72d
|
Merge branch 'master' into shift_reg
|
2021-03-08 09:24:29 -07:00 |
|
Ganesh Gore
|
7a35811430
|
[Flow] Yosys rewrite support
|
2021-03-08 00:35:47 -07:00 |
|
Ganesh Gore
|
67cd9a69b7
|
[Flow] Extended yosys variable subtitution
|
2021-03-08 00:21:07 -07:00 |
Lalit Sharma
|
7945628307
|
Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification
|
2021-03-07 22:25:01 -08:00 |
|
Lalit Sharma
|
6a1ce01084
|
Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
|
2021-03-07 22:02:11 -08:00 |
|
Tarachand Pagarani
|
ce76c58422
|
add shift register test case
|
2021-03-05 09:06:05 -08:00 |
|
Lalit Sharma
|
2b2acae757
|
Adding command to generate verilog file out of yosys run
|
2021-03-05 04:07:02 -08:00 |
|
Lalit Sharma
|
0cbad747a1
|
Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
|
2021-03-04 01:10:47 -08:00 |
|
Lalit Sharma
|
817729ac86
|
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
|
2021-03-01 22:31:15 -08:00 |
|
tangxifan
|
e34380a654
|
Merge branch 'master' into default_net_type
|
2021-03-01 08:38:58 -07:00 |
|
Lalit Sharma
|
ea4aee8cb2
|
For time-being yosys script running in no_adder mode.
|
2021-02-28 22:07:23 -08:00 |
|
Lalit Sharma
|
0038496d9c
|
Replacing -openfpga with -family qlf_k4n8
|
2021-02-28 21:08:47 -08:00 |
|
tangxifan
|
b4b6ada06f
|
[Script] Correct bugs in example scripts using default_net_type
|
2021-02-28 16:31:44 -07:00 |
|
tangxifan
|
86930d63d3
|
[Test] Deploy new test to CI
|
2021-02-28 16:18:46 -07:00 |
|
tangxifan
|
b90a17543d
|
[Test] Add new test case to test default nettype in different verilog syntax
|
2021-02-28 16:16:45 -07:00 |
|
tangxifan
|
9f4d05da67
|
[Test] Bug fix for new test case
|
2021-02-28 16:11:30 -07:00 |
|
tangxifan
|
8cc2c7d924
|
[Script] Bug fix for default net type example script
|
2021-02-28 12:35:44 -07:00 |
|
tangxifan
|
6d419fed41
|
[Test] Deploy verilog default net wire type test case to CI
|
2021-02-28 12:33:48 -07:00 |
|
tangxifan
|
18a7041424
|
[Test] Add default net type test for explicit port mapping
|
2021-02-28 12:31:32 -07:00 |
|
tangxifan
|
0723b79bce
|
[Script] Add example script for verilog default net type
|
2021-02-28 12:29:56 -07:00 |
|
tangxifan
|
27200e3daa
|
[Test] Update regression test cases for fpga verilog
|
2021-02-28 12:24:36 -07:00 |
|
tangxifan
|
ff29cc3dff
|
[Test] Move tests to a test group
|
2021-02-28 12:23:35 -07:00 |
|
tangxifan
|
9cb1ca42fe
|
[Test] Deploy default net type option to test case
|
2021-02-28 12:20:43 -07:00 |
|
tangxifan
|
ae05871b1f
|
[Script] Remove default net type from an example script; Limit it to some test cases
|
2021-02-28 12:19:14 -07:00 |
|
tangxifan
|
d7eb159726
|
[Script] Add default net type option to example openfpga shell scripts
|
2021-02-28 12:08:30 -07:00 |
|
tangxifan
|
0d82e4939c
|
[Test] Use unified quicklogic synthesis script and enable end-of-flow tests
|
2021-02-26 09:35:40 -07:00 |
|
tangxifan
|
744d87cb4e
|
[Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues
|
2021-02-26 09:34:52 -07:00 |
|
tangxifan
|
870d3a0e27
|
Merge branch 'master' into dev
|
2021-02-26 09:28:42 -07:00 |
|
Lalit Sharma
|
1082d3c677
|
Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
|
2021-02-25 23:39:07 -08:00 |