tangxifan
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4e21bbb3f1
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[core] now support constant undriven local wires in verilog writer
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2024-07-04 20:32:56 -07:00 |
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tangxifan
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1dd03d0fdd
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[core] on a new feature to connect undriven pins to ground
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2024-07-04 18:34:39 -07:00 |
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tangxifan
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6d798897fd
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[lib] update vtr
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2024-07-04 14:46:57 -07:00 |
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tangxifan
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f560fb8381
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[core] more verbose
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2024-07-04 14:27:17 -07:00 |
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tangxifan
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a8850d4f0f
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[core] now verbose mode is applicable to more build top module cb instances
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2024-07-04 14:22:30 -07:00 |
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tangxifan
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4b53e57c92
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[core] fixed a bug
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2024-07-04 13:33:04 -07:00 |
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tangxifan
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d2a68ff9c5
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[core] now corner tile are considered as config child
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2024-07-04 13:25:57 -07:00 |
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tangxifan
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b80ed8d15c
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[core] fixed a bug
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2024-07-04 12:58:16 -07:00 |
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tangxifan
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a3723b33b3
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[core] fixed a minor bug
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2024-07-04 12:52:29 -07:00 |
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tangxifan
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a717882304
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[core] now when perimeter_cb is on, I/O pins can access three sides of routing tracks
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2024-07-04 12:44:48 -07:00 |
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tangxifan
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724c14d1f7
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[core] fixed a bug on build top module connections on perimeter gsb when cbs occur
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2024-07-04 11:09:01 -07:00 |
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tangxifan
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550ce0c390
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[core] fixed the bug on build gsb when cbs are on perimeters
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2024-07-04 10:58:44 -07:00 |
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tangxifan
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bc94e08c77
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[lib] update vtr and fixing some bugs in annotate gsb when perimeter_cb is enabled
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2024-07-03 22:28:22 -07:00 |
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tangxifan
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a27325d987
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[core] code format
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2024-07-03 17:05:27 -07:00 |
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tangxifan
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f681c6a903
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[core] update API call due to vtr upgrade
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2024-07-03 17:04:06 -07:00 |
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tangxifan
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a85a6f1674
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[core] code format
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2024-07-01 17:57:10 -07:00 |
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tangxifan
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70428fd969
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[lib] add sanity checks on global port name and clock network's global port name
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2024-07-01 17:56:29 -07:00 |
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tangxifan
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3afb92d6a5
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[core] code format
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2024-06-30 22:48:15 -07:00 |
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tangxifan
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1fd974d544
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[core] fixed a bug where clock network size cannot impact global port on top module
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2024-06-29 17:35:47 -07:00 |
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tangxifan
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4f787a5cfc
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[core] add more debugging message
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2024-06-29 10:54:08 -07:00 |
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tangxifan
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5fa674be24
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[core] fixed the bug on matching global net from pcf
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2024-06-29 10:51:45 -07:00 |
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tangxifan
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8bc37080fa
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[core] debuggging
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2024-06-28 23:06:21 -07:00 |
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tangxifan
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1c69365938
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[core] debugging
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2024-06-28 18:17:38 -07:00 |
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tangxifan
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0de3ff3eb8
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[core] debugging
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2024-06-28 17:16:33 -07:00 |
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tangxifan
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e0b9f7860b
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[core] fixed a bug where counter for gnets are not activated
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2024-06-28 14:10:14 -07:00 |
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tangxifan
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5cfd23747b
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[core] code format
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2024-06-28 13:47:03 -07:00 |
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tangxifan
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f5b6774eb0
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[core] add code comments and fixed some bugs
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2024-06-28 12:21:33 -07:00 |
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tangxifan
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53ba2f0c29
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[core] fixed a critical bug where some switching points are missing
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2024-06-27 15:53:17 -07:00 |
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tangxifan
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5a7f618f29
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[core] debugging
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2024-06-27 15:44:17 -07:00 |
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tangxifan
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f4f487099d
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[core] syntax
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2024-06-27 15:07:48 -07:00 |
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tangxifan
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4185235a69
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[core] now clock routing is based on tree expansion. Unused part can be disconnected
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2024-06-27 15:02:20 -07:00 |
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tangxifan
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e75fd57af2
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[core] refactor codes
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2024-06-27 12:39:18 -07:00 |
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tangxifan
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7892c2340c
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[core] add a new option 'disable_unused_trees' to route clock rr graph
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2024-06-27 12:01:54 -07:00 |
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tangxifan
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6fceb81110
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[core] code format
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2024-06-27 10:19:40 -07:00 |
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tangxifan
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64a7a4ce26
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[core] syntax
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2024-06-27 10:19:14 -07:00 |
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tangxifan
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9ce552495a
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[core] now internal drivers can be routed in dedicated clock network
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2024-06-27 10:17:08 -07:00 |
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tangxifan
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ac1ad52795
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[core] code format
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2024-06-26 22:47:29 -07:00 |
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tangxifan
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5d0b0b9a8c
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[core] now global nets mapping are applied to clock routing
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2024-06-26 22:46:12 -07:00 |
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tangxifan
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d5d9531eec
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[core] comment out buggy codes where global net mapping is not annotated in OpenFPGA
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2024-06-26 21:52:45 -07:00 |
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tangxifan
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59be95b227
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[core] code format
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2024-06-26 17:58:26 -07:00 |
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tangxifan
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59404e5487
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[core] add verbose output
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2024-06-26 17:55:23 -07:00 |
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tangxifan
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576a861b8d
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[core] now skip routing any unused clock tree. Only connect to desired clock pin at programmable blocks
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2024-06-26 17:54:31 -07:00 |
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tangxifan
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3efa97b84e
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[core] support coordinate on clock taps
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2024-06-26 17:40:11 -07:00 |
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tangxifan
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fbece49047
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[core] fixed a bug where unexpected OPINs are added as internal drivers
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2024-06-25 12:07:19 -07:00 |
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tangxifan
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7bcbd8a88b
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[core] code format
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2024-06-25 11:44:50 -07:00 |
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tangxifan
|
3b2c13402a
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[core] syntax
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2024-06-25 11:44:25 -07:00 |
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tangxifan
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31d4b4c402
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[core] now support add internal drivers to clock tree
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2024-06-25 11:27:22 -07:00 |
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tangxifan
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d2053db21c
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[core] removing the restrictions on only 1 clock tree is supported in programmable clock network
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2024-06-21 19:00:01 -07:00 |
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tangxifan
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2193f108ee
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[core] add debugging messages
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2024-06-21 18:42:35 -07:00 |
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tangxifan
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3f08b83b3a
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[core] remove restrictions on 1 clock tree definition
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2024-06-21 17:12:10 -07:00 |