tangxifan
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492db50efe
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[Test] Deploy the new test to basic regression tests
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2021-10-05 10:59:26 -07:00 |
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tangxifan
|
52569f808e
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[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
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2021-10-05 10:57:33 -07:00 |
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tangxifan
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d2859ca1c8
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[Arch] Add an example architecture for multi-region QuickLogic memory bank using shift registers
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2021-10-05 10:56:20 -07:00 |
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tangxifan
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96c1994171
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Merge pull request #21 from RapidSilicon/qlbank_sr
Now QuickLogic Memory Bank Supports WLR signal in shift register-based protocols
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2021-10-04 18:17:17 -07:00 |
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tangxifan
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3efd6840a8
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[Engine] Bug fix for missing WLR ports in auto-generated shift register banks
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2021-10-04 16:58:01 -07:00 |
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tangxifan
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fbef22b494
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[Arch] Bug fix in the example architecture for QL memory bank using WLR and shift registers
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2021-10-04 16:39:53 -07:00 |
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tangxifan
|
13c31cb89c
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[Test] Deploy the qlbanksr_wlr to basic regression tests
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2021-10-04 16:37:49 -07:00 |
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tangxifan
|
fa1908511d
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[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
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2021-10-04 16:36:20 -07:00 |
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tangxifan
|
9a7e0f761a
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[Doc] Add fabric bitstream file format for QL memory bank
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2021-10-04 12:29:49 -07:00 |
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tangxifan
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a01fa7c282
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[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
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2021-10-04 12:09:42 -07:00 |
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tangxifan
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2903f28d24
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Merge pull request #20 from RapidSilicon/qlbank_sr
Support Shift-registers-based QuickLogic's Memory Bank
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2021-10-03 17:23:07 -07:00 |
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tangxifan
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7f75c2b619
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[Test] Deploy shift register -based QL memory bank test case to basic regression test
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2021-10-03 16:06:44 -07:00 |
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tangxifan
|
06b018cfe7
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[FPGA-Bitstream] Reverse bitstream for shift register due to its FIFO nature
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2021-10-03 16:05:33 -07:00 |
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tangxifan
|
2badcb58f2
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[FPGA-Verilog] Fixed a critical bug in verilog testbench generator for QL memory bank using BL/WL register which causes misalignment in shift register loading
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2021-10-03 16:04:47 -07:00 |
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tangxifan
|
28904ff526
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[Engine] Bug fix on wrong port type for shift register chains
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2021-10-03 12:31:58 -07:00 |
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tangxifan
|
756b4c7dc8
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[FPGA-Verilog] Bug fix in estimating the simulation period for QuickLogic memory bank using BL/WL shift registers
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2021-10-03 12:11:20 -07:00 |
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tangxifan
|
3eb601531a
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[FPGA-Verilog] Many bug fixes
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2021-10-02 23:39:53 -07:00 |
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tangxifan
|
d453e6477d
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[FPGA-Verilog] Bug fix
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2021-10-02 22:32:57 -07:00 |
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tangxifan
|
86e7c963f8
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[Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files
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2021-10-02 22:19:20 -07:00 |
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tangxifan
|
02af633acd
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[FPGA-Verilog] Fixed several bugs in testbench generator which caused iVerilog errors
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2021-10-02 22:14:15 -07:00 |
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tangxifan
|
fa7e168137
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[FPGA-Verilog] Now testbench generator connects global shift register clocks to FPGA ports
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2021-10-02 22:08:14 -07:00 |
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tangxifan
|
76d58ebaa0
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[FPGA-Verilog] Move clock generator to generic stimuli and shift register clock period is auto tuned by programming clock period
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2021-10-02 21:48:10 -07:00 |
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tangxifan
|
54ec74d8d2
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[FPGA-Verilog] Bug fix in code generator
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2021-10-02 17:31:37 -07:00 |
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tangxifan
|
32fc0a1692
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[FPGA-Verilog] Upgrading verilog testbench generator for QuickLogic memory bank using BL/WL shift register
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2021-10-02 17:25:27 -07:00 |
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tangxifan
|
f686dd1f60
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[FPGA-Bitstream] Do not reverse for now. Previous solution looks correct
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2021-10-01 23:12:38 -07:00 |
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tangxifan
|
198517a898
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[FPGA-Bitstream] Bug fix on bitstream sequence for QuickLogic memory bank using shift registers
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2021-10-01 19:59:50 -07:00 |
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tangxifan
|
2de6be44d6
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[Engine] Fixed a critical bug which causes bitstream wrong for QuickLogic memory bank when fast configuration is enabled
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2021-10-01 18:27:42 -07:00 |
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tangxifan
|
477c1cd062
|
[Engine] Fixed a critical bug which causes undriven BL/WLs between shift register banks and child modules at the top-level module
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2021-10-01 17:38:26 -07:00 |
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tangxifan
|
977d81679d
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[Engine] Upgrade check codes for WL CCFF
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2021-10-01 17:23:10 -07:00 |
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tangxifan
|
0b06820177
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[HDL] Update the WL CCFF HDL modeling by adding Write-Enable signals
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2021-10-01 17:06:35 -07:00 |
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tangxifan
|
7ba5d27ea7
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[Arch] Reworked example architectures for QuickLogic memory bank using shift registers: Add write-enable signal to WL CCFF model
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2021-10-01 17:02:35 -07:00 |
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tangxifan
|
ff6f7e80f6
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[Flow] Modify simulation setting example for QuickLogic memory bank using separated clks for BL and WL shift registers
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2021-10-01 16:52:06 -07:00 |
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tangxifan
|
9e5debabe1
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[FPGA-Bitstream] Enable fast configuration for QuickLogic memory banks
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2021-10-01 16:23:38 -07:00 |
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tangxifan
|
4f7ab01bf5
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[FPGA-Bitstream] Reworked the bitstream writer to dump BL/WL words separately
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2021-10-01 15:47:13 -07:00 |
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tangxifan
|
2bd2788e77
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[Engine] Upgrading testbench generator to support QuickLogic memory bank with shift registers
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2021-10-01 11:23:40 -07:00 |
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tangxifan
|
cf96d9ff01
|
[Engine] Add programming shift register clock to internal global port data structure
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2021-10-01 11:05:31 -07:00 |
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tangxifan
|
dda147e234
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[Flow] Add an example simulation setting file for defining programming shift register clocks
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2021-10-01 11:04:23 -07:00 |
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tangxifan
|
7b010ba0f4
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[Engine] Support programming shift register clock in XML syntax
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2021-10-01 11:00:38 -07:00 |
|
tangxifan
|
fa57117f50
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[Arch] Update openfpga architecture examples by adding syntax to identify clocks used by shift registers
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2021-10-01 10:19:51 -07:00 |
|
tangxifan
|
96828e456a
|
[FPGA-Bitstream] Fixed a critical bug which cause reshaping bitstream wrong
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2021-09-30 22:07:46 -07:00 |
|
tangxifan
|
4bdff1554d
|
[Engine] Fixed a critical bug which cause BL/WL sharing in shift-register-based memory bank broken
|
2021-09-30 21:20:56 -07:00 |
|
tangxifan
|
33972fc0ec
|
[FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers
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2021-09-30 21:05:41 -07:00 |
|
tangxifan
|
4526133089
|
[FPGA-Bitstream] Add a new data structure that stores fabric bitstream for memory bank using shift registers
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2021-09-30 17:01:02 -07:00 |
|
tangxifan
|
43c569b612
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[FPGA-Bitstream] Encapusulate the data structur storing memory bank fabric bitstream for flatten BL/WL into an object
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2021-09-30 14:47:21 -07:00 |
|
tangxifan
|
4d8019b7c1
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[FPGA-Bitstream] Bug fix in bitstream generator for shift-register-based memory bank
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2021-09-29 22:32:45 -07:00 |
|
tangxifan
|
2d4c200d58
|
[FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists
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2021-09-29 20:56:02 -07:00 |
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tangxifan
|
f456c7e236
|
[Engine] Add a new API to the MemoryBankShiftRegisterBank to access all the unique modules
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2021-09-29 20:34:25 -07:00 |
|
tangxifan
|
b87b7a99c5
|
[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
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2021-09-29 20:21:46 -07:00 |
|
tangxifan
|
8f0ae937bc
|
[Engine] Upgraded fabric generator to support single shift register bank per configuration region for QuickLogic memory bank
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2021-09-29 16:57:49 -07:00 |
|
tangxifan
|
41cc375746
|
[Arch] define default CCFF model in ql bank example architecture that uses shift registers
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2021-09-29 16:34:40 -07:00 |