AurelienUoU
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85c9f26a9f
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Update documentation about cmake version and graphical interface
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2020-01-22 20:46:49 -07:00 |
tangxifan
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07ad32241a
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Merge branch 'refactoring' into dev
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2020-01-22 20:30:26 -07:00 |
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tangxifan
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7909a1ad82
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update title for openfpga shell
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2020-01-22 20:29:57 -07:00 |
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tangxifan
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523f9ac391
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start implement openfpga shell and use vpr as a macro
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2020-01-22 20:20:10 -07:00 |
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tangxifan
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f6a36e8f76
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Merge branch 'refactoring' into dev
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2020-01-22 19:52:31 -07:00 |
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tangxifan
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e983966a08
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add macro function support to openfpga shell and update unit test
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2020-01-22 19:30:36 -07:00 |
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tangxifan
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6309ef2db4
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Merge branch 'refactoring' into dev
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2020-01-22 17:21:21 -07:00 |
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tangxifan
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558f0bb1bd
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bug fixing in shell echo messages and add a test script
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2020-01-22 17:11:24 -07:00 |
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tangxifan
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9b79bb2114
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Merge branch 'refactoring' into dev
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2020-01-22 16:52:23 -07:00 |
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tangxifan
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bb8ef9614f
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change to namespace openfpga and bug fixed to avoid easy crash due to wrong options
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2020-01-22 16:49:32 -07:00 |
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tangxifan
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f8c5c1a117
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update shell with new function binding strategy and new help desk print-out
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2020-01-22 16:05:14 -07:00 |
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tangxifan
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7073e4d082
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add shell unit test
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2020-01-21 22:59:53 -07:00 |
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tangxifan
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4f26e2519f
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add shell interface and command execution
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2020-01-21 20:46:24 -07:00 |
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tangxifan
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363ab382e5
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add shell data structure
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2020-01-21 17:24:49 -07:00 |
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tangxifan
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b53897b838
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add how-to-use for command data structure
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2020-01-20 22:53:11 -07:00 |
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tangxifan
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7a5b36fe52
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Add echo command and unit test for command parser
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2020-01-20 20:31:16 -07:00 |
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tangxifan
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3ae80a192f
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add command echo functionality for mini shell
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2020-01-20 19:42:43 -07:00 |
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tangxifan
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acdb3818c2
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start developing mini shell for open fpga
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2020-01-20 18:14:24 -07:00 |
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tangxifan
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16752b7e39
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update on sample arch
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2020-01-20 12:42:08 -07:00 |
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tangxifan
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4c5917ac97
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Merge branch 'refactoring' into dev
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2020-01-19 15:01:09 -07:00 |
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tangxifan
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07994d424c
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add XML parser and writer for direct connection
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2020-01-19 15:00:19 -07:00 |
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tangxifan
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10336cbe67
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add XML parser and writer for routing circuit definition for OpenFPGA architecture
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2020-01-19 14:44:27 -07:00 |
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tangxifan
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ebe46d15a9
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add XML parser, writer and linker for configuration protocol data structure
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2020-01-18 21:19:20 -07:00 |
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tangxifan
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9693c3a12d
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add XML writer for simulation setting object
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2020-01-18 16:41:42 -07:00 |
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tangxifan
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bc3130d196
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add XML parser for simulation setting
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2020-01-18 15:40:20 -07:00 |
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tangxifan
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2a902c7e55
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add mutators to simulation setting data structure
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2020-01-18 14:07:37 -07:00 |
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tangxifan
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0de9908d52
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add accessors to simulation setting data structure
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2020-01-18 12:51:25 -07:00 |
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tangxifan
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7a46c85cb0
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reorganize and clean-up sample architecture
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2020-01-18 10:50:15 -07:00 |
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tangxifan
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c9da3d5207
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-01-17 20:05:33 -07:00 |
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tangxifan
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ab1b1b7e02
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add XML writer for technology library
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2020-01-17 20:02:56 -07:00 |
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tangxifan
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df68dddb2a
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Merge branch 'refactoring' into dev
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2020-01-17 19:03:57 -07:00 |
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tangxifan
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8f2936af54
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finish XML parser for technology library
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2020-01-17 17:43:55 -07:00 |
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tangxifan
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e54760c677
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add XML parsing for transistors and RRAM parameters in technology library
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2020-01-17 17:32:42 -07:00 |
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tangxifan
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d48a888804
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add XML parsing for design parameters in technology library
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2020-01-17 17:22:09 -07:00 |
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tangxifan
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de0bcc96fb
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add missing file about XML parsers for technology library
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2020-01-17 17:16:32 -07:00 |
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tangxifan
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d58186507c
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add XML parsing for device model library settings
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2020-01-17 17:15:58 -07:00 |
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tangxifan
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88a96673e3
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rename some methods in technology library and start building associated XML parser
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2020-01-17 16:44:57 -07:00 |
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tangxifan
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6a17abf257
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-01-17 15:36:22 -07:00 |
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tangxifan
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b1501223cc
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bug fixed in SDC for CBs and SBs: remove useless module names
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2020-01-17 15:33:50 -07:00 |
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tangxifan
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4bb0da5a69
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bug fixing for direct connection when pin duplication is applied
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2020-01-17 15:33:50 -07:00 |
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tangxifan
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d4b5171fa2
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add comments to technology library
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2020-01-17 15:31:44 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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c68f373917
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Merge pull request #41 from LNIS-Projects/dev
bug fixed in SDC for CBs and SBs: remove useless module names
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2020-01-17 15:29:00 -07:00 |
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tangxifan
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313922f03f
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add internal linker to technology library
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2020-01-17 15:04:00 -07:00 |
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tangxifan
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edaaa00c1d
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added mutators for technology library
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2020-01-17 14:46:09 -07:00 |
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tangxifan
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6b703a4fc5
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add accessors to technology library data structure
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2020-01-17 13:34:32 -07:00 |
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tangxifan
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622ba9bb8c
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bug fixed in SDC for CBs and SBs: remove useless module names
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2020-01-17 11:24:33 -07:00 |
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tangxifan
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771f2d9c37
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developing data structure TechnologyLibrary to store technology-related information
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2020-01-17 10:17:15 -07:00 |
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tangxifan
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aa070b2a41
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further clean-up sample arch.xml
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2020-01-17 09:38:35 -07:00 |
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tangxifan
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910c69d7e5
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clean up and reorganize XML about technology library
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2020-01-17 09:24:58 -07:00 |
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tangxifan
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5c69f57559
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sample_arch:move cmos/rram variation to technology library XML nodes
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2020-01-16 20:58:45 -07:00 |