tangxifan
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e9d29e27e5
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[Tool] Bug fix
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2021-07-02 15:32:30 -06:00 |
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tangxifan
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6e6c3e9fa4
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[Tool] Patch the critical bug in the use of signal polarity in pin constraints
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2021-07-02 15:26:21 -06:00 |
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tangxifan
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b83eef47b4
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[Tool] Bug fix for testbench generation without self checking codes
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2021-06-29 16:27:29 -06:00 |
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tangxifan
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7ac7de789e
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[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
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2021-06-29 15:26:40 -06:00 |
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tangxifan
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77dddaeb39
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[Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions
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2021-06-29 14:26:33 -06:00 |
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tangxifan
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21d1519658
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[Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option
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2021-06-24 16:56:28 -06:00 |
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tangxifan
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d98be9f87b
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[Tool] Remove icarus requirement on vcd writing in Verilog testbenches; Since vcd writing commands are standard Verilog
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2021-06-04 16:45:00 -06:00 |
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tangxifan
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0b49c22682
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[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
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2021-04-18 16:11:11 -06:00 |
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tangxifan
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73461971d2
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[Tool] Bug fix for printing single-bit ports in Verilog netlists
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2021-02-28 16:12:57 -07:00 |
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tangxifan
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d2defebee9
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[Tool] Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
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2021-01-22 16:42:13 -07:00 |
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tangxifan
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75b99b78e9
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[Tool] Now testbench generator consider pin constraints in generating clock sources for benchmarks
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2021-01-19 17:38:51 -07:00 |
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tangxifan
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87b2c1f3b8
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[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
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2021-01-15 12:01:53 -07:00 |
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tangxifan
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852f5bb72e
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[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
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2021-01-14 15:38:24 -07:00 |
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tangxifan
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9cc9e45b4b
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[Tool] Apply a dirty fix to Verilog testbench generator so that multi-clock testbench can be generated
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2021-01-13 15:13:19 -07:00 |
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tangxifan
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4aa6264b1c
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[Tool] Rework simulation time period to be sync with actual stimuli
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2020-12-02 22:58:13 -07:00 |
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tangxifan
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c82f01b3ab
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[Tool] Use conditional operator in signal initialization to eliminate all the warning messages
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2020-11-23 15:50:23 -07:00 |
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tangxifan
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e644545f21
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[Doc] Remove signal initialization for select ports of MUXes and Pass-gates; Use urandom to generate just-fit random vectors
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2020-11-23 15:02:06 -07:00 |
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tangxifan
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3b2a4c5387
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[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
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2020-11-22 20:25:03 -07:00 |
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tangxifan
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37c10f0cb5
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[Tool] Add mappable I/O support and enhance I/O support
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2020-11-04 20:21:49 -07:00 |
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tangxifan
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e4d974c5c8
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[Tool] Split io location mapping builder from fabric builder
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2020-11-02 18:27:34 -07:00 |
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tangxifan
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bba476fef4
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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1e2226e1c3
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now use explicit port mapping in the verilog testbenches for reference benchmarks
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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ff9cc50527
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relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
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2020-03-27 20:09:50 -06:00 |
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tangxifan
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80bb2baae5
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start verification and bug fixing
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2020-02-28 14:29:01 -07:00 |
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tangxifan
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ae899f3b11
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bug fixed for clock names
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2020-02-27 16:51:55 -07:00 |
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tangxifan
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9b769cd8e4
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bug fix for using renamed i/o names
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2020-02-27 16:37:20 -07:00 |
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tangxifan
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25e0583636
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add io location map data structure and start porting verilog testbench generator
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2020-02-26 17:10:57 -07:00 |