Commit Graph

115 Commits

Author SHA1 Message Date
tangxifan 43afaca17c [Doc] Add more details about the new syntax 2021-07-01 23:51:54 -06:00
tangxifan 0851075bc9 [Doc] Update documentation about the new feature in pin constraint file 2021-07-01 23:47:36 -06:00
tangxifan ac9046b7d2 [Doc] Remove ``define_simulation.v`` since it is no longer needed. 2021-06-29 15:38:35 -06:00
tangxifan 30027b8c15 [Doc] Update doc to deprecate anything related to '--support_icarus_simulator' and '--include_signal_init' 2021-06-25 15:27:15 -06:00
tangxifan 11d0283771 [Doc] Remove option '--support_icarus_simulator'. Add option '--embed_bitstream' 2021-06-25 15:11:12 -06:00
tangxifan 507f5ee54c [Doc] Update documentation about time unit support in writing simulation file 2021-06-25 10:34:43 -06:00
tangxifan 8e2ba718d0 [Doc] update documentation on the new option '--testbench_type' 2021-06-25 10:16:48 -06:00
tangxifan 779437cd37 [Doc] Update documentation to remove out-of-date options related to signal_init 2021-06-24 17:07:15 -06:00
tangxifan 9585e1d3b5 [Doc] Update documentation about 'default_net_type' option in testbench generators 2021-06-14 14:00:34 -06:00
tangxifan b719419931 [Doc] Update documentation on the FPGA-Verilog commands in openfpga shell; Deprecated the 'write_verilog_testbench' command 2021-06-09 16:59:02 -06:00
tangxifan 54a53bc988 [Doc] Update documentation on the minor changes on bitstream file for memory bank protocol 2021-06-07 17:58:00 -06:00
tangxifan 0fee741008 [Doc] Update documentation on the minor changes on fabric bitstream file format 2021-06-07 14:22:35 -06:00
tangxifan c30be6e95e [Doc] Update documentation about the fast configuration for write bitstream command 2021-06-04 20:00:28 -06:00
tangxifan 059e74b4ef [Doc] Add --fast configuration option to documentation for 'write_full_testbench' 2021-06-04 15:17:00 -06:00
tangxifan b83d8826fb [Doc] Update documentation on the testbench organization/waveforms 2021-06-03 16:54:13 -06:00
tangxifan 9bcaa820ae [Doc] Update documentation for the new command 'write_full_testbench' 2021-06-03 16:18:07 -06:00
tangxifan 9b40e74e25 [Doc] Add example circuit models for multipliers and update technical highlight with links to the examples 2021-05-24 15:24:50 -06:00
tangxifan 21a18069a1 [Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples 2021-05-24 14:50:55 -06:00
tangxifan b6b98a75b8 [Doc] Add example circuit model about multi-mode flip-flops; Separate data-path FF circuit model and configuration-chain FF circuit model; 2021-05-24 13:03:40 -06:00
tangxifan 24f83f0058 [Doc] Update documentation about the new command 'report_bitstream_distribution' 2021-05-07 11:54:33 -06:00
tangxifan 1bae59dc6a [Doc] Update documentation for the write_io_mapping command 2021-04-27 14:54:57 -06:00
tangxifan 62dc5a3856 [Doc] Update documentation about the new syntax introduced for pin binding between operating modes and physical modes 2021-04-24 16:02:24 -06:00
tangxifan 2e1cc5499d [Doc] Add disclaimer for limitations when using repack pin constraints 2021-04-21 14:14:54 -06:00
tangxifan 9b3dcc65bd [Doc] Add new bitstream setting syntex 'interconnect' to documentation 2021-04-19 16:37:21 -06:00
tangxifan e5b47b7d3d [Doc] Update documentation on the changes on fabric bitstream file formats 2021-04-10 15:45:39 -06:00
tangxifan 19b2641839
Merge branch 'master' into doc_patch 2021-03-15 11:45:32 -06:00
tangxifan fb7d76545e [Doc] Patch the schematic of LUT circuit models to be consistent with netlists 2021-03-15 11:40:09 -06:00
tangxifan ff0faeb285 [Doc] Update documentation about the extended bitstream setting 2021-03-10 21:41:59 -07:00
tangxifan c638e5bde5 [Doc] Update documentation for default net type option 2021-02-28 12:00:55 -07:00
tangxifan 01b9bf2a02 [Doc] Update num_region XML for config protocol 2021-02-18 21:58:30 -07:00
tangxifan 1c4dc9f74b [Doc] Update documentation about the super LUT feature 2021-02-10 11:49:59 -07:00
tangxifan 9c5368f912 [Doc] Correct bugs in compiling latexpdf 2021-02-07 16:17:54 -07:00
AurelienAlacchi 00fc3d7622
Merge pull request #217 from lnis-uofu/dev
Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
2021-02-05 09:53:28 -07:00
tangxifan 9b5c64f35f [Doc] Update documentation about disable_packing syntax 2021-02-04 16:41:24 -07:00
tangxifan d83158654c [Doc] Add a draft documentation about the bitstream setting 2021-02-01 22:33:17 -07:00
tangxifan 0e16638dc2 [Doc] Update documentation about the changes on activity files 2021-01-29 11:49:07 -07:00
tangxifan 78ad9cd000 [Doc] Add version command/option to documentation 2021-01-27 16:06:45 -07:00
tangxifan d53d3963d4 [Doc] Broken link fix in config protocol documentation 2021-01-26 14:05:11 -07:00
tangxifan 9fefe1502f [Doc] Typo fix on write_fabric_key option 2021-01-25 15:18:16 -07:00
tangxifan dd0680246a [Doc] Typo fix on fabric key command 2021-01-25 14:12:40 -07:00
ganeshgore 1ba7e0663f
Merge pull request #176 from lnis-uofu/dev
Documentation Formatting
2021-01-24 21:11:49 -07:00
tangxifan e18c533657 [Doc] Add new openfpga shell command to documentation 2021-01-24 14:48:56 -07:00
tangxifan 815468ac65 [Doc] Add shortcut to call pin constraint option to documentation 2021-01-20 09:20:51 -07:00
tangxifan 977ff52cb1 [Doc] Format openfpga command documentation by using option views 2021-01-19 20:26:38 -07:00
tangxifan e9dc708d66 [Doc] Group file format documentation into a unified section 2021-01-19 19:44:44 -07:00
tangxifan ac8c63553a [Doc] Add file format index file 2021-01-19 18:07:53 -07:00
tangxifan fbb5c0cf8f [Doc] Add pin constraints to documentation 2021-01-19 18:04:45 -07:00
tangxifan c7f02601ab [Doc] Add repack design constraints to documentation 2021-01-17 12:59:46 -07:00
tangxifan c4d3e7c50c [Doc] Update documentation for the new XML syntax in simulation settings 2021-01-15 12:30:26 -07:00
tangxifan 0c808bec41 [Doc] Add clarification for defining multi-bit global tile ports 2021-01-09 20:00:16 -07:00