tangxifan
|
6adf439081
|
Merge remote-tracking branch 'upstream/master'
|
2021-09-01 14:19:00 -07:00 |
Will
|
c31c1d8b04
|
Accept absolute project paths as inputs to the 'run_fpga_task.py' script.
|
2021-08-13 11:08:09 -04:00 |
|
tangxifan
|
8baf60603a
|
[Script] Patching the run_fpga_task.py on pin constraint files
|
2021-07-02 15:59:29 -06:00 |
Ganesh Gore
|
c67807868c
|
[bugFix] Benchamrk variable declaration
|
2021-07-02 15:26:39 -06:00 |
|
Ganesh Gore
|
edd5be2cae
|
[CI] Added testcase for benchmark variable
|
2021-07-02 12:51:34 -06:00 |
|
Ganesh Gore
|
1de1f2f2e2
|
[FLOW] Variable in capital case
|
2021-07-01 22:26:00 -06:00 |
|
Ganesh Gore
|
81f9dff9ff
|
[Flow] Allows benchmark specific var declaraton
|
2021-07-01 22:19:53 -06:00 |
komaljaved-rs
|
6559f71082
|
added ci_scripts
|
2021-07-01 15:07:37 +05:00 |
|
tangxifan
|
7119075253
|
[Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated
|
2021-06-29 15:52:42 -06:00 |
|
tangxifan
|
fd580bb36f
|
[Script] Update script to keep back compatibility: local run directory is different only for those benchmarks sharing the same top module name
|
2021-06-22 11:45:23 -06:00 |
|
tangxifan
|
f9e66e1bae
|
[Script] Support benchmarks with same top module names in openfpga flow script; Now each benchmark local run directory has a unique name;
|
2021-06-21 15:27:12 -06:00 |
|
tangxifan
|
fce84e564d
|
[Script] Patch on missing string to show in error message
|
2021-06-18 11:20:35 -06:00 |
|
tangxifan
|
0e01177cf0
|
[Script] Now openfpga flow script output detailed error message when task is not found
|
2021-06-18 11:01:45 -06:00 |
|
tangxifan
|
781880ed93
|
[Script] Add tolerance options to check qor script
|
2021-03-23 12:26:33 -06:00 |
|
tangxifan
|
adfbd28a7a
|
[Script] Add a simple QoR checker
|
2021-03-23 11:06:16 -06:00 |
|
tangxifan
|
e1f8b252b1
|
Merge branch 'master' into yosys_heterogeneous_block_support
|
2021-03-16 20:05:21 -06:00 |
|
tangxifan
|
090f483a11
|
[Script] Now task-run script support the use of env variables openfpga_path in yosys scripts
|
2021-03-16 16:45:57 -06:00 |
|
tangxifan
|
b42541d84e
|
[Flow] Support multiple iterations in rewriting yosys scripts
|
2021-03-10 14:10:35 -07:00 |
|
tangxifan
|
035043d0d8
|
[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr
|
2021-03-10 13:36:11 -07:00 |
|
tangxifan
|
5d46537b5b
|
[Script] Allow users to specify custom post-synthesis verilog for simulation
|
2021-03-10 11:45:55 -07:00 |
|
tangxifan
|
aafd87c3f9
|
[Flow] Update flow-run to support custom yosys rewrite scripts
|
2021-03-10 11:36:29 -07:00 |
|
tangxifan
|
131643dcc0
|
[Flow] Bug fix for yosys rewrite function in openfpga flow-run script
|
2021-03-08 21:08:55 -07:00 |
|
ganeshgore
|
b860722893
|
Fixed parameter ys_rewrite_params name bug
|
2021-03-08 10:34:39 -07:00 |
|
ganeshgore
|
52de55e7eb
|
Merge branch 'master' into ganesh_dev
|
2021-03-08 10:15:06 -07:00 |
|
Ganesh Gore
|
7a35811430
|
[Flow] Yosys rewrite support
|
2021-03-08 00:35:47 -07:00 |
|
Ganesh Gore
|
67cd9a69b7
|
[Flow] Extended yosys variable subtitution
|
2021-03-08 00:21:07 -07:00 |
Lalit Sharma
|
6a1ce01084
|
Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
|
2021-03-07 22:02:11 -08:00 |
|
Lalit Sharma
|
0cbad747a1
|
Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
|
2021-03-04 01:10:47 -08:00 |
|
Lalit Sharma
|
817729ac86
|
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
|
2021-03-01 22:31:15 -08:00 |
|
tangxifan
|
d85d6e964e
|
Merge pull request #227 from watcag/master
Standard-cell flow
|
2021-02-17 10:11:34 -07:00 |
|
tangxifan
|
a819375f69
|
[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
|
2021-02-16 16:53:13 -07:00 |
Tarachand Pagarani
|
3a587f663a
|
copy yosys output file in case power analysis setting is off
|
2021-02-15 02:36:02 -08:00 |
Nachiket Kapre
|
b4185f7e8c
|
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA
|
2021-02-08 21:11:30 -05:00 |
|
Nachiket Kapre
|
2344cdcabc
|
merge
|
2021-02-08 21:11:28 -05:00 |
|
tangxifan
|
1ce94040da
|
Merge pull request #221 from lnis-uofu/flow_dev
[Flow] Support multi-user environment for running task
|
2021-02-08 12:43:57 -07:00 |
|
Ganesh Gore
|
ede5f8ed58
|
[Flow] Support multi-user enviroment for running task
|
2021-02-07 22:11:04 -07:00 |
|
Ganesh Gore
|
6cdc31f073
|
[Flow] ACE is optional duign flow script
|
2021-02-03 19:07:48 -07:00 |
|
Ganesh Gore
|
df4a397470
|
[Cleanup] Removed deadcode
|
2021-02-03 10:35:14 -07:00 |
|
Ganesh Gore
|
0b82b6439b
|
[Regression] Upgraded runtime enviroment to python3.8
|
2021-01-26 16:40:45 -07:00 |
|
ganeshgore
|
289d9d2169
|
[Bugfix] Honors yosys_tmpl parameter in flow script
|
2020-12-03 12:24:24 -07:00 |
|
ganeshgore
|
59bd7d0f18
|
[Flow] Changed substitute to safe_sustitute option
|
2020-11-25 22:09:36 -07:00 |
|
ganeshgore
|
fefba0db59
|
Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
|
2020-11-25 17:29:53 -07:00 |
|
ganeshgore
|
1554f583b7
|
[Flow] Now support explicit variable file for task
|
2020-11-25 17:22:41 -07:00 |
|
tangxifan
|
521accdc88
|
Merge pull request #104 from lukefahr/disp_fix
FLOW: fixed display flag
|
2020-10-07 09:54:06 -06:00 |
|
tangxifan
|
7b12c28e4f
|
Merge pull request #102 from lukefahr/blif_bug
Fixed blif formatting bug
|
2020-10-06 20:05:02 -06:00 |
Andrew Lukefahr
|
33bbe0ec48
|
FLOW: fixed display flag
|
2020-10-06 20:52:28 -04:00 |
|
Andrew Lukefahr
|
d68427e47b
|
Fixed blif formatting bug
|
2020-10-06 20:46:50 -04:00 |
|
Andrew Lukefahr
|
2d92a1f1af
|
Edits to enable basic run_fpga_flow.py
|
2020-10-02 10:18:10 -04:00 |
|
tangxifan
|
dbd93e429d
|
now pro_blif.pl can accept customized clock name
|
2020-08-19 09:43:44 -06:00 |
|
ganeshgore
|
747c062f86
|
BugFix : Flow script accepts extra OpenFPGA arguments
|
2020-07-27 18:10:43 -06:00 |