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OpenFPGA
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71 Commits

Author SHA1 Message Date
tangxifan e1f8b252b1 Merge branch 'master' into yosys_heterogeneous_block_support 2021-03-16 20:05:21 -06:00
tangxifan 090f483a11 [Script] Now task-run script support the use of env variables openfpga_path in yosys scripts 2021-03-16 16:45:57 -06:00
tangxifan b42541d84e [Flow] Support multiple iterations in rewriting yosys scripts 2021-03-10 14:10:35 -07:00
tangxifan aafd87c3f9 [Flow] Update flow-run to support custom yosys rewrite scripts 2021-03-10 11:36:29 -07:00
tangxifan 131643dcc0 [Flow] Bug fix for yosys rewrite function in openfpga flow-run script 2021-03-08 21:08:55 -07:00
ganeshgore b860722893
Fixed parameter ys_rewrite_params name bug 2021-03-08 10:34:39 -07:00
ganeshgore 52de55e7eb
Merge branch 'master' into ganesh_dev 2021-03-08 10:15:06 -07:00
Ganesh Gore 7a35811430 [Flow] Yosys rewrite support 2021-03-08 00:35:47 -07:00
Ganesh Gore 67cd9a69b7 [Flow] Extended yosys variable subtitution 2021-03-08 00:21:07 -07:00
Lalit Sharma 6a1ce01084 Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS 2021-03-07 22:02:11 -08:00
Lalit Sharma 0cbad747a1 Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family 2021-03-04 01:10:47 -08:00
Lalit Sharma 817729ac86 Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables 2021-03-01 22:31:15 -08:00
tangxifan a819375f69 [Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled 2021-02-16 16:53:13 -07:00
Tarachand Pagarani 3a587f663a copy yosys output file in case power analysis setting is off 2021-02-15 02:36:02 -08:00
Ganesh Gore 6cdc31f073 [Flow] ACE is optional duign flow script 2021-02-03 19:07:48 -07:00
Ganesh Gore df4a397470 [Cleanup] Removed deadcode 2021-02-03 10:35:14 -07:00
ganeshgore 289d9d2169 [Bugfix] Honors yosys_tmpl parameter in flow script 2020-12-03 12:24:24 -07:00
ganeshgore 59bd7d0f18 [Flow] Changed substitute to safe_sustitute option 2020-11-25 22:09:36 -07:00
ganeshgore fefba0db59 Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev 2020-11-25 17:29:53 -07:00
ganeshgore 1554f583b7 [Flow] Now support explicit variable file for task 2020-11-25 17:22:41 -07:00
tangxifan 521accdc88
Merge pull request #104 from lukefahr/disp_fix 
FLOW:  fixed display flag
 2020-10-07 09:54:06 -06:00
tangxifan 7b12c28e4f
Merge pull request #102 from lukefahr/blif_bug 
Fixed blif formatting bug
 2020-10-06 20:05:02 -06:00
Andrew Lukefahr 33bbe0ec48 FLOW: fixed display flag 2020-10-06 20:52:28 -04:00
Andrew Lukefahr d68427e47b Fixed blif formatting bug 2020-10-06 20:46:50 -04:00
Andrew Lukefahr 2d92a1f1af Edits to enable basic run_fpga_flow.py 2020-10-02 10:18:10 -04:00
ganeshgore 747c062f86 BugFix : Flow script accepts extra OpenFPGA arguments 2020-07-27 18:10:43 -06:00
ganeshgore 3b6cd885f3 BugFix: Fixed yosys_vpr with openFPGA_Shell 2020-07-22 11:57:04 -06:00
ganeshgore 41585436c8 Added external_fabric_key_file key 2020-06-12 15:37:12 -06:00
ganeshgore c1b73efa62 Added support for simulation setting file in the task flow 2020-06-10 23:12:30 -06:00
ganeshgore 689c4a3e19 BugFix: The filename in the previous commit 2020-04-15 12:44:22 -06:00
ganeshgore 7f37bf1441 Added formal verification support to fpga_flow script 2020-04-15 12:24:51 -06:00
ganeshgore f6b3c5854a Bugfix : 
+ OpenFPGA template variables update
+ Default path for the verilog netlist
 2020-04-11 16:45:22 -06:00
ganeshgore 8ea272dc2c Patched the OpenFPGA shell execution bug 2020-04-08 21:28:14 -06:00
ganeshgore 583a4d8767 Fixed bug in openfpga_flow script 2020-04-08 12:04:08 -06:00
ganeshgore ea4122a8a4 Updated openfpga_flow and task file to support sheel run 2020-04-06 00:34:36 -06:00
ganeshgore d1d3446568 backedup partial upgrade for fpga_flow script 2020-04-05 11:36:24 -06:00
ganeshgore 46bb5ef9d0 Added disp option in openfpga_flow, Default is --nodisp 2020-01-23 10:04:38 -07:00
ganeshgore f0bed1244c Added blif file folding before VPR run 2020-01-09 16:50:34 -07:00
ganeshgore 74b650e9e1 Added fpga_x2p_duplicate_grid_pin option 2019-12-30 12:25:28 -07:00
ganeshgore d1e260f54f Spice related option added 2019-12-30 12:16:04 -07:00
Ganesh Gore 6bb11918dc Updated modelsim and collected result 2019-11-16 19:10:04 -07:00
Ganesh Gore 333d10c94c Added vpr_fpga_verilog_print_simulation_ini option 2019-11-15 14:26:57 -07:00
Ganesh Gore a880802803 Bug Fix: Corrected read VPR stat filename 2019-11-01 20:51:05 -06:00
Ganesh Gore 595d2d3070 Simple argument shuffle 2019-11-01 18:21:26 -06:00
Ganesh Gore 81180939ca Bug fix: Missing exit_if_fail flag in fpga_flow script 2019-10-31 09:56:57 -06:00
Ganesh Gore c034b871bb Made activity file independent of power option 2019-10-15 16:08:25 -06:00
Ganesh Gore eaf8ecee86 added _vpr.txt subscript to vpr log files 2019-10-15 16:07:34 -06:00
Ganesh Gore cd5fd6ce6c Added explicit checking to VVP execution 2019-09-18 12:14:26 -06:00
Ganesh Gore 169732ccc1 Added verbose option in VVP output 2019-09-17 22:09:37 -06:00
Ganesh Gore 678e3181ba Made compact_routing_hierarchy options uncond 2019-09-16 21:22:13 -06:00