tangxifan
|
6bdfcb0147
|
[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
|
2020-12-05 12:44:09 -07:00 |
|
tangxifan
|
6f18688f0e
|
[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
|
2020-12-05 10:53:01 -07:00 |
|
tangxifan
|
c6ac02d210
|
[FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation
|
2020-09-20 15:21:33 -06:00 |
|
tangxifan
|
544c44fe46
|
[FPGA-SPICE] Add VDD and VSS port to module definition
|
2020-09-20 14:58:15 -06:00 |
|
tangxifan
|
222bc86cbf
|
[FPGA-SPICE] Add auxiliary SPICE netlist writer
|
2020-09-20 12:53:28 -06:00 |
|
tangxifan
|
06c0073a3e
|
[FPGA-SPICE] Add SPICE writer for fpga top module
|
2020-09-20 12:43:48 -06:00 |
|
tangxifan
|
1dfb3e06cc
|
[FPGA-SPICE] add SPICE writer for logic blocks
|
2020-09-20 12:38:24 -06:00 |
|
tangxifan
|
5e78e91fdf
|
[FPGA-SPICE] Add SPICE writer for routing blocks
|
2020-09-20 12:27:48 -06:00 |
|
tangxifan
|
0f25b52907
|
[FPGA-Verilog] code format fix
|
2020-09-20 12:18:22 -06:00 |
|
tangxifan
|
2fae311c8e
|
[FPGA-SPICE] Add SPICE writer for memories
|
2020-09-20 12:14:34 -06:00 |
|
tangxifan
|
f284f6f8d0
|
[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
|
2020-09-20 12:03:10 -06:00 |
|
tangxifan
|
6801d260e9
|
[FPGA-SPICE] Add SPICE writer for LUT
|
2020-09-20 11:58:11 -06:00 |
|
tangxifan
|
0f9fce92b2
|
[FPGA-SPICE] Add SPICE writer for routing multiplexers
|
2020-09-20 11:49:02 -06:00 |
|
tangxifan
|
c7e3d97d1b
|
[FPGA-SPICE] Add supply voltage generator
|
2020-09-20 11:19:06 -06:00 |
|
tangxifan
|
15df9b3893
|
[FPGA-SPICE] Add SPICE subcircuit writer
|
2020-09-19 23:01:44 -06:00 |
|
tangxifan
|
82e137cbe4
|
[FPGA-SPICE] Add wire module SPICE writer
|
2020-09-19 19:31:16 -06:00 |
|
tangxifan
|
1b2762386c
|
[FPGA-SPICE] Bug fix for essential gate netlist writing
|
2020-09-19 16:52:30 -06:00 |
|
tangxifan
|
26a0a769ea
|
[FPGA-SPICE] Split essential gate SPICE netlists into separated files
|
2020-09-19 16:45:26 -06:00 |
|
tangxifan
|
e102e30d19
|
[FPGA-SPICE] Add support for AND/OR logic gate
|
2020-09-19 16:20:21 -06:00 |
|
tangxifan
|
482d90018f
|
[FPGA-SPICE] Create generic PMOS/NMOS instanciation function
|
2020-09-19 15:33:28 -06:00 |
|
tangxifan
|
3262ceb276
|
[FPGA-SPICE] Bug fix for pass gate transistor sizing
|
2020-09-19 15:24:40 -06:00 |
|
tangxifan
|
aa078f079c
|
[FPGA-SPICE] Restructured SPICE netlist writers for atom circuits to avoid large cpp files
|
2020-09-19 15:20:19 -06:00 |
|
tangxifan
|
f5dadca884
|
[FPGA-SPICE] Optimize the print-out of SPICE ports
|
2020-09-19 15:07:48 -06:00 |
|
tangxifan
|
51d423e4db
|
[FPGA-SPICE] Add pass-gate SPICE netlist writer
|
2020-09-19 14:59:00 -06:00 |
|
tangxifan
|
a3d22c56e3
|
bug fix in FPGA-SPICE
|
2020-07-24 19:51:32 -06:00 |
|
tangxifan
|
fd3e947c6d
|
update FPGA_SPICE to support max width for transistors and multi-bin
|
2020-07-24 17:52:31 -06:00 |
|
tangxifan
|
73e2b857a3
|
add buffer support to FPGA-SPICE
|
2020-07-24 15:54:18 -06:00 |
|
tangxifan
|
a4a38f8156
|
support multi-bit power gate ports in FPGA-SPICE
|
2020-07-22 20:04:39 -06:00 |
|
tangxifan
|
f573fa3ee0
|
move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
|
2020-07-22 18:47:12 -06:00 |
|
tangxifan
|
97cca72590
|
add spice support on power gated inverters
|
2020-07-22 18:21:11 -06:00 |
|
tangxifan
|
b5fd6aa859
|
add inverter subckt writer to FPGA-SPICE
|
2020-07-17 13:01:08 -06:00 |
|
tangxifan
|
462fc0d04e
|
add spice transistor wrapper writer
|
2020-07-05 14:50:29 -06:00 |
|
tangxifan
|
b38ee0e8be
|
add spice writer functions
|
2020-07-05 13:58:05 -06:00 |
|
tangxifan
|
81171a8f97
|
start transplanting FPGA-SPICE
|
2020-07-05 12:10:12 -06:00 |