tangxifan
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1faacfa3cf
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keep autocheck testbenches underwater now, bring them back when refactored. Start plugging in the new engine
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2019-10-29 14:23:09 -06:00 |
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tangxifan
|
7c116aac2f
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added Verilog generation for preconfig top module
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2019-10-29 13:54:35 -06:00 |
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tangxifan
|
10491c4291
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bring single mode test case online with bug fixing
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2019-10-28 17:04:10 -06:00 |
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tangxifan
|
fe005f1f56
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remove legacy codes for Verilog formal verification testbench generation
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2019-10-28 15:21:14 -06:00 |
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tangxifan
|
c047fd3cb2
|
plugged in the refactored formal verification Verilog testbench using random vectors
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2019-10-28 15:10:29 -06:00 |
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tangxifan
|
ccabe4ce2a
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refactoring Verilog formal verification top testbench using random vectors
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2019-10-28 14:45:51 -06:00 |
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tangxifan
|
55eea6c4d5
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rename files to be clear
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2019-10-27 20:12:48 -06:00 |
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tangxifan
|
35073f48cf
|
add runtime profiling to module graph builders
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2019-10-27 19:10:21 -06:00 |
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tangxifan
|
2b06cfc3cf
|
added fabric bitstream generator and fixed critical bugs in top module graph
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2019-10-27 18:47:33 -06:00 |
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tangxifan
|
f116351831
|
add instance name for each pb graph node
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2019-10-26 17:25:45 -06:00 |
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tangxifan
|
7649d9228e
|
fixed bugs in refactored bitstream generation
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2019-10-26 16:40:14 -06:00 |
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tangxifan
|
0a9c89be0b
|
add bitstream writers and start debugging
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2019-10-26 12:41:23 -06:00 |
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tangxifan
|
3310bac65b
|
refactored grid bitstream generation
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2019-10-25 21:49:47 -06:00 |
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tangxifan
|
4b7a9dfa63
|
add instance name correlation between module and bitstream generation
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2019-10-25 13:06:48 -06:00 |
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tangxifan
|
0b687669c8
|
affliate configuration bitstream to sb blocks
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2019-10-25 10:42:12 -06:00 |
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tangxifan
|
c38513c838
|
add local encoder support in bitstream generation refactoring
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2019-10-24 22:49:24 -06:00 |
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tangxifan
|
97193794c4
|
correct bugs in organizing child modules in top-level module
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2019-10-24 21:27:42 -06:00 |
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tangxifan
|
838173f3c4
|
start refactoring bitstream generator
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2019-10-24 21:01:11 -06:00 |
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tangxifan
|
13c62fdcf8
|
add more methods to bitstream manager (renamed from bitstream context)
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2019-10-24 15:43:29 -06:00 |
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tangxifan
|
f26dbfe080
|
add instance name for top-level modules to ease readability
|
2019-10-23 20:24:52 -06:00 |
|
tangxifan
|
2787a07f0d
|
start refactoring bitstream generation
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2019-10-23 17:34:21 -06:00 |
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tangxifan
|
a18f1305cd
|
add configurable child list to module manager
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2019-10-23 15:44:13 -06:00 |
|
tangxifan
|
12162a02bc
|
critical bug fixing for compact routing hierarchy and top module generation
|
2019-10-23 14:20:04 -06:00 |
|
tangxifan
|
fb2f003d5b
|
add top module generation and refactored verilog generation for top module
|
2019-10-23 12:16:58 -06:00 |
|
tangxifan
|
dafab3907e
|
refactored routing module generation and verilog writing
|
2019-10-23 11:46:55 -06:00 |
|
tangxifan
|
89c8d089a3
|
add grid module generation
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2019-10-22 16:14:11 -06:00 |
|
tangxifan
|
9cf8683acd
|
add module generation for memories
|
2019-10-22 15:31:08 -06:00 |
|
tangxifan
|
3cf7950bc1
|
add wire module generation and simplify Verilog generation for wires
|
2019-10-21 20:20:34 -06:00 |
|
tangxifan
|
c076da9bab
|
remove redundant codes
|
2019-10-21 18:48:34 -06:00 |
|
tangxifan
|
81093f0db6
|
add lut module generation and simplify Verilog generation codes
|
2019-10-21 17:54:15 -06:00 |
|
tangxifan
|
f002f7e30f
|
add const 0 and 1 module Verilog generation
|
2019-10-21 14:17:09 -06:00 |
|
tangxifan
|
bd37f0d542
|
correct bugs in decoder data port alignment to memory ports of multiplexing structure
|
2019-10-21 13:16:15 -06:00 |
|
tangxifan
|
fe433f3e50
|
bug fixed for local encoders and module nets creation
|
2019-10-21 12:23:00 -06:00 |
|
tangxifan
|
b2f57ecf81
|
plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
|
2019-10-21 00:00:30 -06:00 |
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tangxifan
|
520e145af2
|
move mux_lib to fpga_x2p_setup
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2019-10-19 19:13:52 -06:00 |
|
tangxifan
|
04f0fbebf7
|
plug in module graph to feed verilog writers
|
2019-10-18 21:59:22 -06:00 |
|
tangxifan
|
b1cafcdbde
|
add missing files
|
2019-10-18 21:04:35 -06:00 |
|
tangxifan
|
fbe56a06c4
|
add decoder module builders
|
2019-10-18 21:01:10 -06:00 |
|
tangxifan
|
7c1bce4b59
|
add module builders for essential gates
|
2019-10-18 20:41:05 -06:00 |
|
tangxifan
|
3b82d62d03
|
start developing module graph builders
|
2019-10-18 20:02:02 -06:00 |
|
tangxifan
|
db38f21412
|
add netlist manager class
|
2019-10-18 17:59:03 -06:00 |
|
tangxifan
|
8c1158fc5c
|
refactor memory organization at the top-level module
|
2019-10-18 15:33:25 -06:00 |
|
tangxifan
|
cfec8d70ab
|
improved refactoring on clb2clb connection by considering flexible arch
|
2019-10-18 11:20:09 -06:00 |
|
tangxifan
|
4171a674b1
|
refactored clb2clb direct connects for cross-column/row
|
2019-10-17 23:06:59 -06:00 |
|
tangxifan
|
190449c06f
|
refactoring top-level module with clb2clb direct connection
|
2019-10-17 17:29:04 -06:00 |
|
tangxifan
|
945e138e62
|
debugged the gsb-grid connection in top module.
|
2019-10-15 22:02:25 -06:00 |
|
tangxifan
|
c9d8311a93
|
bug fixing for grid-gsb connections in top module when using compact routing
|
2019-10-15 18:00:55 -06:00 |
|
tangxifan
|
6a13120208
|
rename grid modules to be clear
|
2019-10-15 16:28:46 -06:00 |
|
tangxifan
|
071757dc52
|
add module nets to connect grids and sbs
|
2019-10-15 16:08:51 -06:00 |
|
tangxifan
|
4b56b755f2
|
refactored instanciation of routing modules in top module
|
2019-10-14 21:06:10 -06:00 |