tangxifan
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f80e58c753
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developing a in-house tokenizer
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2019-08-09 16:36:22 -06:00 |
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tangxifan
|
3d7adb3dd9
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start developing parsers for delay values
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2019-08-09 15:52:28 -06:00 |
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tangxifan
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6b5ac2e1ef
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add timing graph builder for circuit models
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2019-08-09 12:45:03 -06:00 |
Ganesh Gore
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b82369dd96
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Added first draft of fpga_task script
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2019-08-09 00:17:06 -06:00 |
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tangxifan
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c8d04c4f00
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plug in fast look-up builder
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2019-08-08 21:20:28 -06:00 |
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Ganesh Gore
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0cc439f76c
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Working lattice benchmark unclean commit
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2019-08-08 18:08:39 -06:00 |
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tangxifan
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158c67075e
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built a conversion from spice_models to circuit_library and plug in
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2019-08-08 17:25:27 -06:00 |
Baudouin Chauviere
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0b46adb5ef
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Correction to the explicit Verilog for FPGAs above 2x2
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2019-08-08 15:17:43 -06:00 |
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tangxifan
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e19485bbb7
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add more accessors and more to be added when plug into framework
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2019-08-08 14:16:29 -06:00 |
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tangxifan
|
ad8c33e1ba
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complete the mutators
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2019-08-08 11:33:11 -06:00 |
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tangxifan
|
5b0c9572c3
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add mutators for delay_info
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2019-08-07 21:19:16 -06:00 |
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tangxifan
|
03a64e2ad8
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complete the mutators for ports
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2019-08-07 20:54:27 -06:00 |
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tangxifan
|
9f8c7a3fc7
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adding port mutators
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2019-08-07 17:47:39 -06:00 |
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tangxifan
|
ed4642a23f
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adding basic mutators
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2019-08-07 17:12:05 -06:00 |
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tangxifan
|
38962c4607
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adding member functions for circuit library
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2019-08-07 15:45:27 -06:00 |
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tangxifan
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74da4ed51a
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start creating the class for circuit models
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2019-08-07 11:38:45 -06:00 |
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tangxifan
|
f57495feba
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Now we can also auto-generate the Verilog for a mux2 std cell
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2019-08-06 15:19:01 -06:00 |
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tangxifan
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55bfaf271d
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Merge branch 'dev' into std_map_support
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2019-08-06 14:38:19 -06:00 |
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tangxifan
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afa468a442
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hotfix in minor Verilog generation
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2019-08-06 14:17:57 -06:00 |
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tangxifan
|
b207050b03
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minor fix in documentation
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2019-08-06 14:17:57 -06:00 |
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tangxifan
|
b4f3dfc82d
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bug fixing for local encoder's bitstream generation
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2019-08-06 14:17:57 -06:00 |
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tangxifan
|
fc93a4941a
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update documentation
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2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
7603850d72
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complete documentation for new features
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2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
3a490fdd59
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bug fixing on the port map alignment
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2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
890ff05628
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bug fixing and get ready for testing
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2019-08-06 14:17:56 -06:00 |
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tangxifan
|
c08c136844
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set a working range for the encoders
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2019-08-06 14:17:56 -06:00 |
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tangxifan
|
386bddacd1
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updated bitstream generator for local encoders
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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557b1af633
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add Verilog generation for local encoders, bitstream upgrade TODO
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2019-08-06 14:17:56 -06:00 |
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tangxifan
|
003883b13b
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implementing the local encoders
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2019-08-06 14:17:55 -06:00 |
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tangxifan
|
fb2ca66ce9
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start adding submodules of local encoders to multiplexer
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2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
33f3a991b5
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init effort to start developing mux local encoders
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2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
7748340314
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hot fix on tutorial
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2019-08-06 14:17:55 -06:00 |
|
Baudouin Chauviere
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0a5546e43c
|
Fully functional
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2019-08-05 14:06:07 -06:00 |
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tangxifan
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2291c52fab
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-30 16:54:55 -06:00 |
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tangxifan
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8a046394f8
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add documentation for multi-mode configurable block support
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2019-07-30 16:47:41 -06:00 |
AurelienUoU
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40b7f1cc53
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-07-29 11:45:23 -06:00 |
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tangxifan
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c95fea268d
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Merge pull request #25 from LNIS-Projects/dev
Dev
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2019-07-27 15:20:53 -06:00 |
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tangxifan
|
716c3c63c3
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-27 15:06:06 -06:00 |
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AurelienUoU
|
7d469d8b4f
|
Docker try 2
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2019-07-22 13:06:46 -06:00 |
|
AurelienUoU
|
52b754f9c1
|
Update
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2019-07-22 10:14:03 -06:00 |
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AurelienUoU
|
0854161a63
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Docker update
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2019-07-22 09:42:31 -06:00 |
|
AurelienUoU
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64a67dceaf
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Merge branch 'documentation' of https://github.com/LNIS-Projects/OpenFPGA into documentation
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2019-07-18 16:34:47 -06:00 |
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AurelienUoU
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f4e999ef6d
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Correct error in demo, set a new generated ff_${benchmark}.v file rather than overwrite
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2019-07-18 16:33:23 -06:00 |
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tangxifan
|
73d6d5264a
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-18 13:40:19 -06:00 |
|
tangxifan
|
434c0d9683
|
hot fix on tutorial
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2019-07-18 13:39:47 -06:00 |
|
tangxifan
|
e52deac6ad
|
Merge pull request #20 from LNIS-Projects/dev
Add fracturable LUT documentation
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2019-07-18 09:06:32 -04:00 |
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tangxifan
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ac1c5bb59a
|
Merge pull request #16 from LNIS-Projects/egiacomin-patch-2
Update building.md
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2019-07-17 18:49:11 -04:00 |
|
Xifan Tang
|
173440ffc3
|
retry
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2019-07-17 18:46:54 -04:00 |
|
Xifan Tang
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8226f42d3d
|
use hfill to place image inline
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2019-07-17 18:46:14 -04:00 |
|
Xifan Tang
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a80199057d
|
logo placement
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2019-07-17 18:43:17 -04:00 |