Xifan Tang
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37abd8af40
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try to place inline logo
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2019-07-17 18:40:26 -04:00 |
|
Xifan Tang
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f3ed949c4b
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retry placing images
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2019-07-17 18:36:49 -04:00 |
|
Xifan Tang
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b104de0263
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resize logo again
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2019-07-17 17:56:06 -04:00 |
|
Xifan Tang
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b850610cea
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resize logo to fit
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2019-07-17 17:55:10 -04:00 |
|
Xifan Tang
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17308621bd
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resize logo on README
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2019-07-17 17:53:36 -04:00 |
|
Xifan Tang
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af335dff66
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Merge branch 'documentation' of https://github.com/LNIS-Projects/OpenFPGA into documentation
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2019-07-17 17:51:45 -04:00 |
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Xifan Tang
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afd78604c9
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Merge branch 'dev' into documentation: resolved conflicts and add logo files
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2019-07-17 17:50:11 -04:00 |
|
Xifan Tang
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6af0d277a2
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hot fix on fpga logo
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2019-07-17 17:48:01 -04:00 |
|
Xifan Tang
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5bec11bd6e
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try to add logo
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2019-07-17 17:46:25 -04:00 |
|
Xifan Tang
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e7b40f06b0
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Add documentation for fracturable LUTs
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2019-07-17 15:21:07 -04:00 |
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tangxifan
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8a92a3b589
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Merge pull request #19 from LNIS-Projects/egiacomin-patch-5
Update how2use.md
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2019-07-17 14:34:23 -04:00 |
egiacomin
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922e40131f
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Update how2use.md
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2019-07-17 12:33:15 -06:00 |
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tangxifan
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a16dae6d8c
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Merge pull request #18 from LNIS-Projects/egiacomin-patch-4
Egiacomin patch 4
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2019-07-17 14:33:12 -04:00 |
AurelienUoU
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5947818761
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Typo correction
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2019-07-17 12:23:06 -06:00 |
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egiacomin
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1da04b9c3a
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Update tutorial_index.md
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2019-07-17 12:19:57 -06:00 |
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egiacomin
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95b56f31d7
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Update README.md
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2019-07-17 12:11:38 -06:00 |
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egiacomin
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68c459482f
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Update building.md
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2019-07-17 12:09:59 -06:00 |
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egiacomin
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f10bce826a
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Update README.md
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2019-07-17 12:07:40 -06:00 |
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egiacomin
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77e1480a4c
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Merge pull request #14 from LNIS-Projects/dev
Dev - Critical bug fixing and add support for MUX2 standard cell mapping
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2019-07-17 11:55:52 -06:00 |
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tangxifan
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32e3a556b9
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bug fixing herited from explicit mapping
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2019-07-17 09:26:05 -06:00 |
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tangxifan
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8b8e18a8de
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bug fixing for mux subckt names
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2019-07-17 08:59:57 -06:00 |
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tangxifan
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a2505ff16a
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turn on std cell explicit port map
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2019-07-17 08:36:09 -06:00 |
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tangxifan
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dcc96bf7f5
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bug fixing
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2019-07-17 08:25:52 -06:00 |
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tangxifan
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6e1d49d74e
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start to support direct mapping to MUX2 standard cells
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2019-07-17 07:54:23 -06:00 |
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AurelienUoU
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8b7f20f1ba
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Merge branch 'dev' into documentation
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2019-07-17 07:33:30 -06:00 |
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AurelienUoU
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5b8eaab93f
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Docker test 2.3
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2019-07-16 20:13:46 -06:00 |
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tangxifan
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4672311aae
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Merge pull request #13 from LNIS-Projects/dev
Dev
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2019-07-16 22:10:04 -04:00 |
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AurelienUoU
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ca2c840e1e
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Docker test 2.2
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2019-07-16 20:04:04 -06:00 |
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AurelienUoU
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b31fb0ab83
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Docker test 2.1
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2019-07-16 19:56:13 -06:00 |
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AurelienUoU
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31e6ee3ee1
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Docker test 2
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2019-07-16 19:47:53 -06:00 |
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AurelienUoU
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1822e2059a
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Docker building test
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2019-07-16 19:32:06 -06:00 |
AurelienAlacchi
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3aa0a4a5e6
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Merge pull request #12 from LNIS-Projects/tangxifan-patch-1
Update building.md
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2019-07-16 21:20:38 -04:00 |
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tangxifan
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d6dfc29508
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Now we use the ace from VTR
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2019-07-16 17:00:09 -06:00 |
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AurelienUoU
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938f2ec68c
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Update Dockerfile
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2019-07-16 16:30:00 -06:00 |
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tangxifan
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61026dc623
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Update building.md
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2019-07-16 16:58:11 -04:00 |
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tangxifan
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954a8c14f7
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remove redundant files
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2019-07-16 14:55:04 -06:00 |
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tangxifan
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da8745b163
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Update README.md
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2019-07-16 16:51:52 -04:00 |
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tangxifan
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0c68642aad
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Update README.md
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2019-07-16 16:49:15 -04:00 |
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tangxifan
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e9154b1f74
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-16 14:42:45 -06:00 |
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tangxifan
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b807fdb38a
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Merge branch 'tileable_routing' into dev
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2019-07-16 14:38:18 -06:00 |
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tangxifan
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be255edc68
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now use vtr_assert in ace
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2019-07-16 14:37:19 -06:00 |
Baudouin Chauviere
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712eccfa30
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Merge branch 'dev', remote-tracking branch 'origin' into explicit_verilog
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2019-07-16 13:37:52 -06:00 |
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Baudouin Chauviere
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65122d04b3
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-16 13:37:21 -06:00 |
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tangxifan
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115411941b
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-16 13:15:45 -06:00 |
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AurelienUoU
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509c1d2c80
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Link path correction
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2019-07-16 13:13:58 -06:00 |
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Baudouin Chauviere
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69014704ef
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Explicit verilog final push
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2019-07-16 13:13:30 -06:00 |
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AurelienAlacchi
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b0017cdbdf
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Merge pull request #11 from LNIS-Projects/dev
Dev
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2019-07-16 13:08:24 -06:00 |
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Baudouin Chauviere
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e602006a07
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-16 12:45:13 -06:00 |
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AurelienUoU
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fe218fc207
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Tutorial update
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2019-07-16 11:52:24 -06:00 |
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AurelienUoU
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a04555419a
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Typo fix
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2019-07-16 07:30:25 -06:00 |