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5187 Commits

Author SHA1 Message Date
tangxifan 671188dfa4 [FPGA-Verilog] Now support big/little-endian in bus group 2022-02-18 23:05:03 -08:00
tangxifan feaaeea787
Merge pull request #539 from lnis-uofu/bus_support 
Support buses in Verilog testbenches
 2022-02-18 16:48:52 -08:00
tangxifan a78d091606
Merge branch 'master' into bus_support 2022-02-18 15:51:03 -08:00
tangxifan 8116141210 [Doc] Update documentation on the bus group feature 2022-02-18 15:46:25 -08:00
tangxifan 68644ea0f6 [Test] Add the new test to basic regression tests 2022-02-18 15:44:07 -08:00
tangxifan f0ce1e79a3 [Test] Added a new test to validate bus group in full testbench 2022-02-18 15:43:21 -08:00
tangxifan 790715f46a [FPGA-Verilog] Fixing bugs when using bus group in full testbench generator 2022-02-18 15:41:35 -08:00
tangxifan fe9e0ff977 [Test] Add the new test to basic regression tests 2022-02-18 15:38:53 -08:00
tangxifan c897a64ad5 [Script] Add a new example script to test full testbenches using bus group features 2022-02-18 15:37:42 -08:00
tangxifan 223575cf3e [Test] Added a new test for bus group on full testbenches 2022-02-18 15:33:29 -08:00
tangxifan 85c893c94c [Test] Add new test to basic regression tests 2022-02-18 15:30:08 -08:00
tangxifan 5ab84e1861 [Test] Add a new test for bus group 2022-02-18 15:29:33 -08:00
tangxifan b4d59fdd1e [Test] Update bus group file due to little and big endian conversion during yosys/vpr 2022-02-18 15:02:08 -08:00
tangxifan 36543f7f2f [Script] Support simplified rewriting for Yosys on output verilog 2022-02-18 14:54:39 -08:00
tangxifan 401f673f16 [FPGA-Verilog] Streamline codes by using APIs 2022-02-18 14:47:36 -08:00
tangxifan c16ea8d082 [FPGA-Verilog] Fixing bugs in naming wires in verilog testbenches 2022-02-18 14:34:32 -08:00
tangxifan a4dc86a33d [FPGA-Verilog] Now output atom block name removal has a dedicated function 2022-02-18 14:30:46 -08:00
tangxifan f5dd89bbd9 [FPGA-Verilog] Fixed bugs in preconfigured wrapper generator when bus group is used 2022-02-18 14:08:03 -08:00
tangxifan 8ba3d06392 [Test] Fixed bugs in simulation settings 2022-02-18 12:36:22 -08:00
tangxifan 94fea84a40 [Lib] Fix a bug in memory allocation 2022-02-18 12:36:03 -08:00
tangxifan a4d5172b7c [Test] Fixed bugs that causes VPR failed 2022-02-18 12:31:29 -08:00
tangxifan 43d852d8a1 [Test] Add the bus group test case to basic regression tests 2022-02-18 12:27:25 -08:00
tangxifan 7176037bc4 [Test] Added a new test about bus group 2022-02-18 12:26:00 -08:00
tangxifan 73e6ee964d [Script] Add a new example script showing how to use bus group features 2022-02-18 12:25:34 -08:00
tangxifan 0d620888ab [FPGA-Verilog] Now instance can output bus ports with all the pins 2022-02-18 12:03:26 -08:00
tangxifan aa375fd7a4 [FPGA-Verilog] Fixed a bug due to the use of bus group in testbench generator 2022-02-18 11:31:11 -08:00
tangxifan 6da0ede9b0 [FPGA-Verilog] Adding bus group support to all Verilog testbench generators 2022-02-17 23:48:44 -08:00
tangxifan c96f0d199d [FPGA-Verilog] Adding bus group support in Verilog testbenches 2022-02-17 23:14:28 -08:00
tangxifan 37d8617a5c [Doc] Update due to new options 2022-02-17 19:45:37 -08:00
tangxifan 38601f325b [Engine] Add bus group to OpenFPGA core 2022-02-17 17:28:55 -08:00
tangxifan e60d7d12b7 [Lib] Fixed a bug in writer 2022-02-17 17:12:07 -08:00
tangxifan 4b3f906f11 [Lib] Fixed all the syntax errors 2022-02-17 17:09:03 -08:00
tangxifan 8d4087f893
Merge pull request #538 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-02-17 16:28:09 -08:00
github-actions[bot] 0a6421a1fc Updated Patch Count 2022-02-18 00:24:29 +00:00
tangxifan 27627bf5b4 [Lib] Add an example XML for bus group unit tests 2022-02-17 16:22:01 -08:00
tangxifan 0d7e949166 [Lib] Add unit test for bus group 2022-02-17 16:21:12 -08:00
tangxifan 76cf4e1662 [Lib] Add reader and writer for bus group 2022-02-17 16:17:37 -08:00
tangxifan 1edaa04715 [Lib] Adding XML parser for the bus group 2022-02-17 15:50:44 -08:00
tangxifan 4a78bcf5d3 [Doc] update file format about bus group 2022-02-17 15:15:05 -08:00
tangxifan b44701bc2c [Lib] Adding the 1st version of bus group data structure 2022-02-17 15:02:37 -08:00
tangxifan f5e0d685cf [Doc] Adjust figure width 2022-02-17 14:29:09 -08:00
tangxifan 796428d848 [Doc] Add documentation about bus group file format 2022-02-17 14:22:21 -08:00
tangxifan 9d00308166
Merge pull request #537 from lnis-uofu/dependabot/submodules/yosys-plugins-0fa6d61 
Bump yosys-plugins from `503b979` to `0fa6d61`
 2022-02-17 09:20:48 -08:00
dependabot[bot] 6f5f48c83e
Bump yosys-plugins from `503b979` to `0fa6d61` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `503b979` to `0fa6d61`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](503b9791c1...0fa6d614fe)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-02-17 07:25:22 +00:00
tangxifan 68b8d05741
Merge pull request #536 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-02-16 16:29:26 -08:00
github-actions[bot] cd4f4c7558 Updated Patch Count 2022-02-17 00:20:26 +00:00
tangxifan 64bf2e01c3
Merge pull request #535 from lnis-uofu/dependabot/submodules/yosys-plugins-503b979 
Bump yosys-plugins from `ea7411a` to `503b979`
 2022-02-16 10:16:45 -08:00
dependabot[bot] 30d045dce0
Bump yosys-plugins from `ea7411a` to `503b979` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `ea7411a` to `503b979`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](ea7411a915...503b9791c1)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-02-16 07:21:25 +00:00
tangxifan eec0da5327
Merge pull request #533 from lnis-uofu/counter 
Add initial conditions to counter benchmarks
 2022-02-15 18:33:45 -08:00
tangxifan e67f8ad8b2 [FPGA-Verilog] Now full testbench does not check any output vectors during configuration phase 2022-02-15 17:19:50 -08:00